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BR93LC66F Datasheet(PDF) 7 Page - Rohm |
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BR93LC66F Datasheet(HTML) 7 Page - Rohm |
7 / 12 page 7 Memory ICs BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV CS SK DI DO ∗1 ∗2 D14 D15 D0 D1 D14 D15 0 High-Z 1 1 0 0 A7 A6 A1 A0 1 2 411 12 27 28 ∗1 If the first data input following the rise of the start bit CS is "1", the start bit is acknowledged. Also, if a "1" is input following several zeroes in succession, the "1" is recognized as the start bit, and subsequent operation commences. This applies also to all commands described subsequently. ∗2 Address auto increment function: These ICs are equipped with an address auto increment function which is effective only during reading operations. With this function, if the SK clock is input following execution of one of the above reading commands, data is read from upper addresses in succession. CS is held in HIGH state during automatic incrementing. Fig.2 Read cycle timing (READ) (4) Reading (Figure 2) When the read command is acknowledged, the data (16 bits) for the input address is output serially. The data is synchronized with the SK rise during A0 acqui- sition and a “0” (dummy bit) is output. All further data is output in synchronization with the SK pulse rises. (5) Write enable (Figure 3) These ICs are set to the write disabled state by the in- ternal reset circuit when the power is turned on. Therefore, before performing a write command, the write enable command must be executed. When this command is executed, it remains valid until a write disable command is issued or the power supply is cut off. However, read commands can be used in either the write enable or write disable state. (6) Write (Figure 4) This command writes the input 16-bit data (D15 to D0) to the specified address (A7 to A0). Actual writing of the data begins after CS falls (following the 27th clock pulse after the start bit input), and DO is in the Acquire state. STATUS is not detected if CS = LOW after the time tE / W. When STATUS is detected (CS = HIGH), no com- mands are accepted while DO is LOW (BUSY). There- fore, no commands should be input during this period. 10 0 1 1 CS SK DI DO High-Z Fig.3 Write enable cycle timing |
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