BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F /

Memory Ics

BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV

(5) Write protect (WP)

(6) ACK signal

The acknowledge signal (ACK signal) is determined by software and is used to indicate whether or not a data transfer

is proceeding normally. The transmitting device, whether the master or slave, opens the bus after an 8-bit data output

(

µ-COM when a write or read command of the slave address input ; this IC when reading data).

For the receiving device during the ninth clock cycle, SDA is set to LOW and an acknowledge signal (ACK signal) is

sent to indicate that it received the 8-bit data (this IC when a write command or a read command of the slave address

input,

µ-COM when a read command data output).

The ICs output a LOW acknowledge signal (ACK signal) after recognizing the start condition and slave address (8

bits).

When data is being write to the ICs, a LOW acknowledge signal (ACK signal) is output after the receipt of each 8 bits

of data (word address and write data).

When data is being read from the IC, 8bits of data (read data) are output and the IC waits for a returned LOW

acknowledge signal (ACK signal). When an acknowledge signal (ACK signal) is detected and a stop condition is not

sent from the master (

µ-COM) side, the IC continues to output data. If an acknowledge signal (ACK signal) is not

detected, the IC interrupts the data transfer and ceases reading operations after recognizing the stop condition (stop

bit). The IC then enters the waiting or standby state.

(See Fig.3 for acknowledge signal (ACK signal) response.)

1

8

9

SCL

SDA

SDA

Start condition

(start bit)

Acknowledge signal

(ACK signal)

(from

µ-COM)

output data)

(

µ−COM

(IC output data)

Fig.3 Acknowledge (ACK signal) response

(during write and read slave address input)