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BU8871F Datasheet(PDF) 6 Page - Rohm

Part # BU8871F
Description  DTMF receiver for telephones
Download  12 Pages
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Manufacturer  ROHM [Rohm]
Direct Link  http://www.rohm.com
Logo ROHM - Rohm

BU8871F Datasheet(HTML) 6 Page - Rohm

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185
Communication ICs
BU8871F
FCircuit operation
(1) An overview of operation
A DTMF signal is supplied to the INPUT pin and applied
to a pair of 6th-order bandpass filters, which separate the
DTMF signal into its high (COL) and low (ROW) frequen-
cies. The separated tones are converted into square
waves and fed to a digital detector. (See the block dia-
gram.)
The digital detector checks the two tones to see if they
are within the valid DTMF frequency bands. If they are,
it sends a DETECT signal to the steering circuit, and
sends the appropriate column and row address signals
to a code converter.
The code converter encodes the received and detected
DTMF signal, and outputs an ENABLE signal to the
steering circuit.
Based on the DETECT and ENABLE signals, the steer-
ing circuit outputs an Early Steering (ESt) signal, which
sets the ESt pin to HIGH, indicating that a valid DTMF
signal has been detected.
If a series of pulses is input at the ACK pin while ESt is
HIGH, a decoded DTMF signal is output to the SD pin as
a binary code. (See Figure 3 for the overall timing.)
If a pulse sequence is input at the ACK pin, the data is
latched at the rising edge of the first pulse by a parallel-
serial converter, and at the same time, the LSB is output
from the SD pin. Following this, three bits of data are out-
put from the SD pin for each bit of each pulse in the pulse
sequence input from the ACK pin. As a result, a total of
four bits of data are output for the four pulses. (See Fig-
ure 4 for the ACK and SD timing.)
If the pulse sequence input to the ACK pin consists of
three or fewer pulses, the next DTMF input cannot be de-
coded properly. Any ACK pulses in excess of four are ig-
nored until ESt goes HIGH again.
Table 1 shows the format of serial data output from the
SD pin.
(2) Overall timing chart
(3) ACK and SD timing


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