210

Communication ICs

BU8874 / BU8874F

FOperation notes

(1) Power down

When ACK is LOW, the power down mode can be en-

tered by applying a rising edge to the PWDN pin. Current

consumption drops from several seconds to several tens

of seconds after the power down mode has been speci-

fied.

Operation with SD multiple reading is recommended.

(2) Oscillation

Oscillation frequency precision can be a problem with ce-

ramic resonators. Before including a ceramic resonator

in your design, please consult the resonator manufactur-

er to make sure this will not be a problem.

Also, if an external clock is being injected, a DC blocking

capacitor must be inserted. Select a capacitor that will

neither attenuate the frequency components or put an

excessive load on the drive side.

This LSI is not equipped with the power-on reset function. Also, since the internal circuit (flip-flop circuit) becomes unsta-

ble at the rising edge of the power supply, the internal circuit is initialized as shown below by the first DTMF sequence

received after the rising edge of the power supply. Therefore, input four dummy ACK pulses before the DTMF reception.

FElectrical characteristic curves