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Rev. 1.11

- 7 -

n

n

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n TYPICAL APPLICATIONS AND APPLICATION HINTS

Vcc

Reset/

CPU

EXT

GND

CE

SD1

L

PMOS

R1

CE CONTROL

PMOS: HAT1020R (Hitachi), Si3443DV (Siliconix)

L : CD105(Sumida, 27

mH)

SD1

: RB491D (Rohm)

mF(Tantalum Type)

:10

mF(Tantalum Type)

R1 : 100k

W

When you use these ICs, consider the following issues;

l As shown in the block diagram, a parasitic diode is formed in each terminal, each of these diodes is not formed

for load current, therefore do not use it in such a way. When you control the CE pin by another power supply,

Release Voltage from Reset condition must not be more than Output voltage of DC/DC converter.

(Detector Threshold Voltage

´1.07 < Output Voltage of DC/DC converter´0.98

resistor.

l The operation of Latch-type protection circuit is as follows;

When the maximum duty cycle continues longer than the delay time for protection circuit, (Refer to the Electrical

Characteristics) the protection circuit works to shut-down the external Power MOS with its latching operation.

Therefore when an input/output voltage difference is small, the protection circuit may work even at small load

current.

To release the protection state, after disable this IC with a chip enable circuit, enable it again, or restart this IC

with power-on. However, in the case of restarting this IC with power-on, after the power supply is turned off, if

restarted even after power-on.

Output Voltage of DC/DC converter is longer than soft-starting time plus delay time for protection circuit,

l Set external components as close as possible to the IC and minimize the connection between the components

sufficient grounding and reinforce supplying. A large switching current flows through the connection of power

power supply of the IC fluctuates with the switching current. This may cause unstable operation of the IC.