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K4D263238M Datasheet(PDF) 10 Page - Samsung semiconductor |
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K4D263238M Datasheet(HTML) 10 Page - Samsung semiconductor |
10 / 19 page 128M DDR SDRAM K4D263238M - 10 - Rev. 1.3 (Aug. 2001) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extend mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11 and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1 and A6 are used for setting driver strength to weak or matched imped- ance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. “High” on BA0 is used for EMRS. All the other address pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes. A0 DLL Enable 0 Enable 1 Disable BA0 An ~ A0 0 MRS 1 EMRS Figure 7. Extend Mode Register set EXTENDED MODE REGISTER SET(EMRS) Address Bus Extended BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 RFU 1 RFU D.I.C RFU D.I.C DLL Mode Register * RFU(Reserved for future use) should stay "0" during EMRS cycle. A6 A1 Output Driver Impedance Control 0 1 Weak 60% of full drive strength 1 1 Matched impedance 30% of full drive strength |
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