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K4S161622D Datasheet(PDF) 10 Page - Samsung semiconductor |
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K4S161622D Datasheet(HTML) 10 Page - Samsung semiconductor |
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10 / 41 page  K4S161622D CMOS SDRAM DEVICE OPERATIONS ADDRESS INPUTS (A0 ~ A10/AP) : In case x 4 The 21 address bits are required to decode the 2,097,152 word locations are multiplexed into 11 address input pins (A0 ~ A10/ AP). The 11 bit row addresses are latched along with RAS and BA during bank activate command. The 10 bit column addresses are latched along with CAS, WE and BA during read or write command. : In case x 8 The 20 address bits are required to decode the 1,048,576 word locations are multiplexed into 11 address input pins (A0 ~ A10/ AP). The 11 bit row addresses are latched along with RAS and BA during bank activate command. The 9 bit column addresses are latched along with CAS, WE and BA during read or write command. : In case x 16 The 19 address bits are required to decode the 524,288 word locations are multiplexed into 11 address input pins (A0 ~ A10/ AP). The 11 bit row addresses are latched along with RAS and BA during bank activate command. The 8 bit column addresses are latched along with CAS, WE and BA during read or write command. NOP and DEVICE DESELECT When RAS, CAS and WE are high, the SDRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than sin- gle clock cycle like bank activate, burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS, CAS, WE and all the address inputs are ignored. POWER-UP SDRAMs must be powered up and initialized in a pre- defined manner to prevent undefined operations. 1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3. Issue precharge commands for both banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode reg- ister. cf.) Sequence of 4 & 5 is regardless of the order. The device is now ready for normal operation. CLOCK (CLK) The clock input is used as the reference for all SDRAM opera- tions. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between VIL and VIH. During operation with CKE high all inputs are assumed to be in a valid state (low or high) for the duration of set-up and hold time around positive edge of the clock in order to function well Q perform and ICC specifications. CLOCK ENABLE (CKE) The clock enable(CKE) gates the clock onto SDRAM. If CKE goes low synchronously with clock (set-up and hold time are the same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is fro- zen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When all banks are in the idle state and CKE goes low synchronously with clock, the SDRAM enters the power down mode from the next clock cycle. The SDRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least "1CLK + tSS" before the high going edge of the clock, then the SDRAM becomes active from the same clock edge accepting all the input commands. BANK ADDRESS (BA) : In case x 4 This SDRAM is organized as two independent banks of 2,097,152 words x 4 bits memory arrays. The BA input is latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank select BA is latched at bank active, read, write, mode register set and precharge operations. : In case x 8 This SDRAM is organized as two independent banks of 1,048,576 words x 8 bits memory arrays. The BA input is latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank select BA is latched at bank active, read, write, mode register set and precharge operations. : In case x 16 This SDRAM is organized as two independent banks of 524,288 words x 16 bits memory arrays. The BA input is latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank select BA is latched at bank active, read, write, mode register set and precharge operations. |
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