K4S281632B-N

CMOS SDRAM

shrink-TSOP

The K4S281632B-N is 134,217,728 bits synchronous high

data rate Dynamic RAM organized as 4 x 2,097,152 words by

16 bits, fabricated with SAMSUNG

′s high performance CMOS

technology. Synchronous design allows precise cycle control

with the use of system clock I/O transactions are possible on

every clock cycle. Range of operating frequencies, programma-

ble burst length and programmable latencies allow the same

device to be useful for a variety of high bandwidth, high perfor-

mance memory system applications.

• JEDEC standard 3.3V power supply

• LVTTL compatible with multiplexed address

• Four banks operation

• MRS cycle with address key programs

- CAS latency (2 & 3)

- Burst length (1, 2, 4, 8 & Full page)

- Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system

clock.

• Burst read single-bit write operation

• DQM for masking

• Auto & self refresh

• 64ms refresh period (4K cycle)

GENERAL DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM

2M x 16Bit x 4 Banks Synchronous DRAM in sTSOP

Bank Select

Data Input Register

2M x 16

2M x 16

Column Decoder

Latency & Burst Length

Programming Register

LCKE

LRAS

LCBR

LWE

LDQM

CLK

CKE

CS

RAS

CAS

WE

LDQM

LWE

LDQM

DQi

CLK

ADD

LCAS

LWCBR

2M x 16

2M x 16

Timing Register

UDQM

* Samsung Electronics reserves the right to change products or specification without notice.

ORDERING INFORMATION

Part No.

Max Freq.

Interface Package

K4S281632B-NC/L1H

100MHz(CL=2)

LVTTL

54pin

sTSOP(II)

K4S281632B-NC/L1L

100MHz(CL=3)