K4S560432B

CMOS SDRAM

Rev. 0.2 May.2000

The K4S560432B is 268,435,456 bits synchronous high data

rate Dynamic RAM organized as 4 x 16,785,216 words by 4 bits,

fabricated with SAMSUNG's high performance CMOS technol-

ogy. Synchronous design allows precise cycle control with the use

of system clock I/O transactions are possible on every clock cycle.

Range of operating frequencies, programmable burst length and

programmable latencies allow the same device to be useful for a

variety of high bandwidth, high performance memory system

applications.

• JEDEC standard 3.3V power supply

• LVTTL compatible with multiplexed address

• Four banks operation

• MRS cycle with address key programs

-. CAS latency (2 & 3)

-. Burst length (1, 2, 4, 8 & Full page)

-. Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system

clock.

• Burst read single-bit write operation

• DQM for masking

• Auto & self refresh

• 64ms refresh period (8K cycle)

GENERAL DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM

16M x 4Bit x 4 Banks Synchronous DRAM

Bank Select

Data Input Register

16M x 4

16M x 4

Column Decoder

Latency & Burst Length

Programming Register

LCKE

LRAS

LCBR

LWE

LDQM

CLK

CKE

CS

RAS

CAS

WE

DQM

LWE

LDQM

DQi

CLK

ADD

LCAS

LWCBR

16M x 4

16M x 4

Timing Register

ORDERING INFORMATION

Part No.

Max Freq.

Interface Package

K4S560432B-TC/L75

133MHz(CL=3)

LVTTL

54pin

TSOP(II)

K4S560432B-TC/L1H

100MHz(CL=2)

K4S560432B-TC/L1L

100MHz(CL=3)

* Samsung Electronics reserves the right to change products or specification without notice.