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K6T0808C1D-DL55 Datasheet(PDF) 5 Page - Samsung semiconductor |
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K6T0808C1D-DL55 Datasheet(HTML) 5 Page - Samsung semiconductor |
5 / 9 page K6T0808C1D Family CMOS SRAM Revision 1.0 November 1997 CL1) 1. Including scope and jig capacitance AC OPERATING CONDITIONS TEST CONDITIONS (Test Load and Test Input/Output Reference) Input pulse level : 0.8 to 2.4V Input rising and falling time : 5ns Input and output reference voltage : 1.5V Output load (See right) :CL=100pF+1TTL CL=50pF+1TTL AC CHARACTERISTICS (Vcc=4.5~5.5V, K6T0808C1D-L Family:TA=0 to 70 °C, K6T0808C1D-P Family:TA=-40 to 85°C) 1. The parameter is tested with 50pF test load. Parameter List Symbol Speed Bins Units 551)ns 70ns Min Max Min Max Read Read cycle time tRC 55 - 70 - ns Address access time tAA - 55 - 70 ns Chip select to output tCO - 55 - 70 ns Output enable to valid output tOE - 25 - 35 ns Chip select to low-Z output tLZ 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - ns Chip disable to high-Z output tHZ 0 20 0 30 ns Output disable to high-Z output tOHZ 0 20 0 30 ns Output hold from address change tOH 10 - 10 - ns Write Write cycle time tWC 55 - 70 - ns Chip select to end of write tCW 45 - 60 - ns Address set-up time tAS 0 - 0 - ns Address valid to end of write tAW 45 - 60 - ns Write pulse width tWP 40 - 50 - ns Write recovery time tWR 0 - 0 - ns Write to output high-Z tWHZ 0 20 0 25 ns Data to write time overlap tDW 25 - 30 - ns Data hold from write time tDH 0 - 0 - ns End write to output low-Z tOW 5 - 5 - ns DATA RETENTION CHARACTERISTICS Item Symbol Test Condition Min Typ Max Unit Vcc for data retention VDR CS ≥Vcc-0.2V 2.0 - 5.5 V Data retention current IDR Vcc=3.0V, CS ≥Vcc-0.2V L-Ver - 1 15 µA LL-Ver - 0.2 3 Data retention set-up time tSDR See data retention waveform 0 - - ms Recovery time tRDR 5 - - |
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