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K9F1208Q0A-XXB0 Datasheet(PDF) 8 Page - Samsung semiconductor |
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K9F1208Q0A-XXB0 Datasheet(HTML) 8 Page - Samsung semiconductor |
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8 / 45 page  K9F1216U0A-YCB0,YIB0,PCB0,PIB0 FLASH MEMORY 7 K9F1216U0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-YCB0,YIB0,PCB0,PIB0 K9F1208U0A-DCB0,DIB0,HCB0,HIB0 K9F1208Q0A-DCB0,DIB0,HCB0,HIB0 K9F1216Q0A-DCB0,DIB0,HCB0,HIB0 K9F1208U0A-VCB0,VIB0,FCB0,FIB0 PIN DESCRIPTION NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected. Pin Name Pin Function I/O0 ~ I/O7 (K9F1208X0A) I/O0 ~ I/O15 (K9F1216X0A) DATA INPUTS/OUTPUTS The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled. I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper- ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and output. CLE COMMAND LATCH ENABLE The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. ALE ADDRESS LATCH ENABLE The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high. CE CHIP ENABLE The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program or erase opertion. Regarding CE control during read operation, refer to ’Page read’section of Device operation . RE READ ENABLE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. WE WRITE ENABLE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse. WP WRITE PROTECT The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low. R/B READY/BUSY OUTPUT The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. VccQ OUTPUT BUFFER POWER VCCQ is the power supply for Output Buffer. VccQ is internally connected to Vcc, thus should be biased to Vcc. Vcc POWER VCC is the power supply for device. Vss GROUND N.C NO CONNECTION Lead is not internally connected. DNU DO NOT USE Leave it disconnected. |
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