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KM4132G271BQR-7 Datasheet(PDF) 10 Page - Samsung semiconductor |
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KM4132G271BQR-7 Datasheet(HTML) 10 Page - Samsung semiconductor |
10 / 51 page KM4132G271B CMOS SGRAM - 10 Rev. 2.4 (May 1998) SIMPLIFIED TRUTH TABLE (V=Valid, X=Don ′t Care, H=Logic High, L=Logic Low) COMMAND CKEn-1 CKEn CS RAS CAS WE DSF DQM A9 A8 A7~ A0 Note Register Mode Register Set H X L L L L L X OP CODE 1, 2 Special Mode Register Set H 1,2,7 Refresh Auto Refresh H H L L L H L X X 3 Self Refresh Entry L 3 Exit L H L H H H X X X 3 H X X X 3 Bank Active & Row Addr. Write Per Bit Disable H X L L H H L X V Row Address 4, 5 Write Per Bit Enable H 4,5,9 Read & Column Address Auto Precharge Disable H X L H L H L X V L Column Address 4 Auto Precharge Enable H 4, 6 Write & Column Address Auto Precharge Disable H X L H L L L X V L Column Address 4, 5 Auto Precharge Enable H 4,5,6,9 Block Write & Column Addr. Auto Precharge Disable H X L H L L H X V L Column Address 4, 5 Auto Precharge Enable H 4,5,6,9 Burst Stop H X L H H L L X X 7 Precharge Bank Selection H X L L H L L X V L X Both Banks X H Clock Suspend or Active Power Down Entry H L L H H H X X X H X X X Exit L H X X X X X X Precharge Power Down Mode Entry H L L H H H X X X H X X X Exit L H L V V V V X H X X X X DQM H X V X 8 No Operation Command H X L H H H X X X H X X X 1. OP Code : Operand Code A0 ~ A9 : Program keys. (@MRS) A5, A6 : LMR or LCR select. (@SMRS) Color register exists only one per DQi which both banks share. So dose Mask Register. Color or mask is loaded into chip through DQ pin. 2. MRS can be issued only at both banks precharge state. SMRS can be issued only if DQ ′s are idle. A new command can be issued at the next clock of MRS/SMRS. Note : |
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Similar Description - KM4132G271BQR-7 |
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