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KM48V8004B Datasheet(PDF) 7 Page - Samsung semiconductor |
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KM48V8004B Datasheet(HTML) 7 Page - Samsung semiconductor |
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7 / 21 page  KM48V8004B, KM48V8104B CMOS DRAM TEST MODE CYCLE Parameter Symbol -45 -5 -6 Units Note Min Max Min Max Min Max Random read or write cycle time tRC 79 89 109 ns Read-modify-write cycle time tRWC 110 121 145 ns Access time from RAS tRAC 50 55 65 ns 3,4,10,12 Access time from CAS tCAC 17 18 20 ns 3,4,5,12 Access time from column address tAA 28 30 35 ns 3,10,12 RAS pulse width tRAS 50 10K 55 10K 65 10K ns CAS pulse width tCAS 12 10K 13 10K 15 10K ns RAS hold time tRSH 18 18 20 ns CAS hold time tCSH 39 43 50 ns Column Address to RAS lead time tRAL 28 30 35 ns CAS to W delay time tCWD 29 35 39 ns 7 RAS to W delay time tRWD 62 72 84 ns 7 Column Address to W delay time tAWD 40 47 54 ns 7 Hyper Page cycle time tHPC 22 25 30 ns 13 Hyper Page read-modify-write cycle time tHPRWC 52 53 61 ns 13 RAS pulse width (Hyper page cycle) tRASP 50 200K 55 200K 65 200K ns Access time from CAS precharge tCPA 29 33 40 ns 3 OE access time tOEA 17 18 20 ns OE to data delay tOED 13 18 20 ns OE command hold time tOEH 13 18 20 ns ( Note 11 ) |
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