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KM68257C Datasheet(PDF) 6 Page - Samsung semiconductor |
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KM68257C Datasheet(HTML) 6 Page - Samsung semiconductor |
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6 / 10 page  KM68257C/CL CMOS SRAM PRELIMINARY Rev 3.0 - 6 - February-1996 TIMING WAVE FORM OF READ CYCLE(2)(WE=VIH) CS OE Data Out ADD NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V OH or VOL Levels. 4. At any given temperature and voltage condition, t HZ(Max.) is less than t LZ (Min.) both for a given device and from device to device. 5. Transition is measured ±200§Æ from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e. TIMING WAVE FORM OF WRITE CYCLE(1)(OE=Clock) OE CS Data In WE High-Z ADD Data Out Data Valid High-Z(8) 50% 50% Vcc Current Data Valid Icc ISB tRC tAA tCO tHZ(3,4,5) tOHZ tOH tPD tLZ(4,5) tOLZ tOE tPU tWC tAW tCW(3) tWP(2) tAS(4) tDW tDH tOHZ(6) tWR(5) |
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Similar Description - KM68257C |
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