KS5514B -XX

ON SCREEN DISPLAY PROCESSOR

SPECIFICATION

7

98-05-14

OPERATION DESCRIPTION

MEMORY STRUCTURE

After KS5514B records, in DATA RAM and CONTROL REGISTER, the serial DATA that is inputted from MICOM,

in recording to the V-SYNC and H-SYNC signal, mix the COMPOSITE VIDEO signal and the font ROM data that is

mapped to data RAM.

In case that there is no composite video signal that is inputted to KS5514B, the SYNC detector becomes low,

KS5514B makes the blue back signal in dividing the 4fsc signal and the blue back signal is outputted.

The following table is the data structure that is inputted from MICOM.

• Memory address consists of 16 bit

• The data of address 0 ~ 239 are character data which are display on the screen.

• The address 240 ~ 244 are the control registers.

• Don`t care bit : the upper 8 bits (DA8 ~ DAF) in address 0 ~ address 239, the upper 5bits (DAB ~ DAF) in

address 240 ~ address 244

Bit

Addr

0

239

240

241

242

243

244

DAF DAE DAD DAC DAB DAA

DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0

*

*

*

*

*

*

*

*

BLI

C6

C5

C4C3

C2C1

C0

BLI

INT/

NON

HSZ

21

HSZ

20

HSZ

11

HSZ

10

HP5

HP4

HP3 HP2

HP1

HP0

BLI2

VSZ

21

VSZ

20

VSZ

11

VSZ

10

VP5

VP4

VP3 VP2

VP1

VP0

DSP

3

DSP

2

DSP

1

RAM

ERS

TEST TC

LEV

1

LEV

0

PH2

PH1

PH0

-LE

BK

LE

CHA

DSP

ON

BLK

1

BLK

0

BLI

1

BLI

0

EX

YM

BCO

SECAM NT/

PAL

-

PD3 PD2

-

PD0

PC3 PC2

PC1

PC0

C6

C5

C4

C3

C2

C1

C0

·

·

·

·

·

·

·

·

·

·

·

·

(Font ROM Address)

**

*

*

*

*

*

*

**

*

*

*

**

*

*

*

**

*

*

*

**

*

*

*

**

*

*

*