PRODUCT OVERVIEW

S3C72H8/P72H8

1-

6

Table 1-1. S3C72H8 Pin Descriptions (Continued)

Pin Name

Pin

Type

Description

Number

(64-QFP)

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Pin

Circuit

Type

KS0-KS3

I/O

Quasi-interrupt input with falling edge detection

25-28

P6.0-P6.3

D-1

ExtRef

I/O

External Reference input

6

P0.0

D-1

TCL0

I/O

External clock input for timer/counter 0

19

P2.2

D-1

FCL

I/O

External clock input for frequency counter

20

P2.3

D-1

TCLO0

I/O

Timer/counter 0 clock output

21

P3.0

D-1

COM0-COM3

O

LCD common signal output

61-64

–

H-16

SEG0-SEG25

O

LCD segment output

35-60

–

H-16

CA, CB

–

Voltage booster capacitor pins

1, 2

–

–

V

–

Voltage booster output pins (V

output, V

output)

3-5

–

–

C0P, C0N,

C0OUT

I/O

Comparator 0 non-inverting input, inverting input and

output. C0Out can be configured as C-MOS push-pull

or N-Ch open drain output

29-31

P4.0-P4.2

–

C1P, C1N,

C1OUT

I/O

I

Comparator 1 non-inverting input, inverting input and

output. C1Out can be configured as C-MOS push-pull

or N-Ch open drain output

32-34

P4.3-P5.1

–

RESET

–

Reset signal for chip initialization

16

–

B

V

DD

–

Main power supply

9

–

–

V

SS

–

Ground

10

–

–

TEST

–

Test signal input (must be connected to V

13

V

PP

–

SDAT

I/O

Serial data for OTP programming

7

P0.1

SCLK

I/O

Serial clock for OTP programming

8

P0.2

V

PP

–

Power supply pin for EPROM cell writing

13

TEST

NOTE: Pull-up resistors for ports 0, 2, 3, and 6 are automatically disabled if they are configured to output mode.

But pull-up resistors for ports 4 and 5 are retained its state even though they are configured to output mode.