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S5T8554B03 Datasheet(PDF) 7 Page - Samsung semiconductor |
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S5T8554B03 Datasheet(HTML) 7 Page - Samsung semiconductor |
7 / 13 page CODEC FOR DIGITAL ANSWERING PHONE S5T8554B03 7 TIMING DIAGRAM (Continued) Figure 3. NOTE: 1.For Short Frame Sync timing ,FSx and FSR must go high while their respective bit clocks has high level TRANSMISSION CHARACTERISTICS (Unless otherwise specified: Ta = 0 °C to 70°C, Vcc = 5V ± 5%, VBB = −5V ± 5%, GNDA = 0V, f = 1.02kHz Vin = 0dBm0, transmit input amplifier connected for unity-gain, non-inverting ) Characteristic System Test Conditions Min. Typ. Max. Unit Amplitude Response Receive Gain, Absolute GV(ARX) Ta = 25 °C,VCC = 5V, VBB = −5V Input = Digital code sequence for 0dBm0 signal at 1020Hz −1.5 − 1.5 dB Receive Gain, Relative to Gv(RRX) GV(RRX) f = 0Hz to 3000Hz f = 3300Hz f = 3400Hz −0.6 −0.55 −1.5 − 0.5 0.5 1.5 dB Absolute Receive Gain Variations with temperature ∆G V(ARX) / ∆T Ta = 0 °C to 70°C − − ± 0.1 dB |
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