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S5T8809 Datasheet(PDF) 4 Page - Samsung semiconductor |
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S5T8809 Datasheet(HTML) 4 Page - Samsung semiconductor |
4 / 14 page S5T8809 PLL FREQUENCY SYNTHESIZER FOR PAGE 4 PIN DESCRIPTION Pin No Symbol Description 1 OSCI These input / output pins generate the reference frequency. In case of OSCI Pin, external reference frequency can be used through the AC coupling. 2 OSCO 3 VDD2 The highest potential supply terminal that can be supplied up to 2.0 ~ 3.3V. 4 FL Booster signal output for fast locking. 5 PDO The output of RX phase detector terminal for passive loop filter. There are 3-kinds of output signal states according to Rx loop error. 6 VSS Ground terminal 7 Fin Input terminal for the frequency from VCO. Output frequency from VCO was inputted through AC coupling 8 VDD1 Voltage supply terminal for Oscillator and Fin block. This pin can be supplied up to 0.95 ~ 1.5V from VSS. 9 PBC This is an input for programmable bit control which has Schmitt Trigger architecture, Internally biased pull-up. High = 16 Bits N-Divider (Default: ND0 ~ ND15) Low = 18 Bits N-Divider (ND0 ~ ND7) cf) R-divider bits will be changed by the FRC bit of program 10 LD The output of phase detector can be controlled by R-counter register. When the LDC bit of R-counter set to Low, the output will be disabled to reduce a noise problem, but if it is set to High, the output will be enabled to show an lock / unlock status that is the error width between to Ref. signal and the VCO output signal. 11 CLK These pins are controlled by the µ-controller which has Schmitt Trigger architecture, Internally biased pull-down. The features of these pins are as follows; Clock input for 17 or 19-bit Shift Register, Serial data input (it include TEST1, FRC and LDC), and Latch enable input. 12 DATA 13 EN 14 BSB In the BS mode (set to Low), the VDD1 block will be powered off, but the internal latch data is still valid because the VDD2 is supplied continuously. This input has Schmitt Trigger architecture & internally biased pull-up. 15 FLC This is the input pin for Fast Locking Control (FLC) which has Schmitt Trigger architecture, Internally biased pull-down. Low = The Current of PDO Charge pump output is Normal (Default: x1) High = The Current of PDO Charge pump output is increase (x 1.5) 16 TEST This is the input pin for TEST which has Schmitt trigger architecture, Internally biased Pull-down. Low = All block will be operated as normal state (Default) High = LD and FL state will be TES mode |
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