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K7P403622B-HC20 Datasheet(PDF) 10 Page - Samsung semiconductor |
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K7P403622B-HC20 Datasheet(HTML) 10 Page - Samsung semiconductor |
10 / 13 page Rev 1.2 Jul. 2003 - 10 K7P401822B 128Kx36 & 256Kx18 SRAM K7P403622B JTAG Instruction Coding NOTE : 1. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. 2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 3. Bypass register is initiated to VSS when BYPASS instruction is invoked. The Bypass Register also holds serially loaded TDI when exiting the Shift DR states. 4. SAMPLE instruction does not places DQs in Hi-Z. IR2 IR1 IR0 Instruction TDO Output Notes 0 0 0 SAMPLE-Z Boundary Scan Register 1 0 0 1 IDCODE Identification Register 2 0 1 0 SAMPLE-Z Boundary Scan Register 1 0 1 1 BYPASS Bypass Register 3 1 0 0 SAMPLE Boundary Scan Register 4 1 0 1 BYPASS Bypass Register 3 1 1 0 BYPASS Bypass Register 3 1 1 1 BYPASS Bypass Register 3 IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG TAP Controller State Diagram JTAG Block Diagram SRAM CORE BYPASS Reg. Identification Reg. Instruction Reg. Control Signals TAP Controller TDO M2 M1 TDI TMS TCK Test Logic Reset Run Test Idle 0 11 1 1 0 0 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 Select DR Capture DR Shift DR Exit1 DR Pause DR Exit2 DR Update DR Select IR Capture IR Shift IR Exit1 IR Pause IR Exit2 IR Update IR 1 1 1 1 1 The SRAM provides a limited set of IEEE standard 1149.1 JTAG functions. This is to test the connectivity during manufacturing between SRAM, printed circuit board and other components. Internal data is not driven out of SRAM under JTAG control. In conform- ance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP control- ler has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and therefore can be left unconnected. But they may also be tied to VDD through a resistor. TDO should be left unconnected. |
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