FLASH MEMORY

1

K9W4G08U1M

K9W4G16U1M

K9K2G08U0M

K9K2G16Q0M

K9K2G08Q0M

K9K2G16U0M

Document Title

256M x 8 Bit / 128M x 16 Bit NAND Flash Memory

Revision History

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have

any questions, please contact the SAMSUNG branch office near your office.

Revision No

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Remark

Advance

History

1. Initial issue

-min. Value: 7mA -->3mA

-typ. Value: 8mA -->4mA

1. 5th cycle of ID is changed

: 40h --> 44h

1. Add WSOP Package Dimensions.

1. Add two-K9K2GXXU0M-YCB0/YIB0 Stacked Package

1. Min valid block of K9W4GXXU1M-YCB0/YIB0 is changed .

- min. 4016 --> 4036

1.

Each K9K2GXXX0M chip in the K9W4GXXU1M has Maximum 30

invalid blocks.

2. K9W4GXXU1M’s ID is changed

(Before)

(After)

1. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 36)

2. Add the data protection Vcc guidence for 1.8V device - below about 1.1V.

(Page 37)

The min. Vcc value 1.8V devices is changed.

K9K2GXXQ0M : Vcc 1.65V~1.95V --> 1.70V~1.95V

Device

2nd Cycle

3rd cycle

4th Cycle 5th Cycle

K9W4G08U1M

DCh

C3

15h

4Ch

K9W4G16U1M

CCh

C3

55h

4Ch

Device

2nd Cycle

3rd cycle

4th Cycle

5th Cycle

K9W4G08U1M

DAh

C1

15h

44h

K9W4G16U1M

CAh

C1

55h

44h

Draft Date

Aug. 30.2001

Nov. 5.2001

Jan. 23. 2002

May.29.2002

Aug.13.2002

Aug. 22.2002

Nov. 07.2002

Nov. 22.2002

Mar. 6.2003