K6R4004C1D

CMOS SRAM

PRELIMINARY

Rev 1.0

- 6 -

July 2002

Address

Data Out

Previous Valid Data

Valid Data

TIMING DIAGRAMS

NOTES(READ CYCLE)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

levels.

device.

5. Transition is measured

±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

7. Address valid prior to coincident with CS transition low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

WRITE CYCLE*

* The above parameters are also guaranteed at industrial temperature range.

Parameter

Symbol

K6R4004C1D-10

K6R4004C1D-12

Unit

Min

Max

Min

Max

Write Cycle Time

10

-

12

-

ns

Chip Select to End of Write

7

-

8

-

ns

Address Set-up Time

0

-

0

-

ns

Address Valid to End of Write

7

-

8

-

ns

Write Pulse Width(OE High)

7

-

8

-

ns

Write Pulse Width(OE Low)

10

-

12

-

ns

Write Recovery Time

0

-

0

-

ns

Write to Output High-Z

0

5

0

6

ns

Data to Write Time Overlap

5

-

6

-

ns

Data Hold from Write Time

0

-

0

-

ns

End of Write to Output Low-Z

3

-

3

-

ns

Valid Data

High-Z

CS

Address

OE

Data out

50%

50%

Current