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DAC7578SRGER Datasheet(PDF) 6 Page - Texas Instruments |
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DAC7578SRGER Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 55 page  LDAC 1 LDAC2 CLR Low Byte Ack Cycle P S t HD:STA t HD:DAT t SU:DAT t SU:STA t HD:STA S P SCL SDA t LOW t R t F t BUF t SU:STO t 1 t 2 t 3 t 4 t HIGH DAC5578 DAC6578 DAC7578 SBAS496A – MARCH 2010 – REVISED AUGUST 2010 www.ti.com TIMING DIAGRAM (1) Asynchronous LDAC update mode. For more information and details, see the LDAC Functionality section. (2) Synchronous LDAC update mode. For more information and details, see the LDAC Functionality section. Figure 1. Serial Write Operation TIMING REQUIREMENTS (1) At AVDD = 2.7 V to 5.5 V and –40°C to +125°C range (unless otherwise noted). STANDARD FAST HIGH SPEED MODE MODE MODE PARAMETER UNIT MIN MAX MIN MAX MIN MAX SCL frequency, fSCL 0.1 0.4 3.4 MHz Bus free time between STOP and START conditions, tBUF 4.7 1.3 µs Hold time after repeated start, tHDSTA 4 0.6 0.16 µs Repeated Start setup time, tSUSTA 4.7 0.6 0.16 µs STOP condition setup time, tSUSTO 4 0.6 0.16 µs Data hold time, tHDDAT 0 0 0 ns Data setup time, tSUDAT 250 100 10 ns SCL clock LOW period, tLOW 4700 1300 160 ns SCL clock HIGH period, tHIGH 4000 600 60 ns Clock/Data fall time, tF 300 300 160 ns Clock/Data rise time, tR 1000 300 160 ns LDAC pulse width LOW time, t1 40 10 1.2 µs SCL falling edge to LDAC falling edge for asynchronous LDAC update, t2 20 5 0.6 µs LDAC falling edge to SCL falling edge for synchronous LDAC update, t3 360 90 10.5 µs CLR pulse width LOW time, t4 40 10 1.2 µs (1) See the Serial Write Operation timing diagram. 6 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DAC5578 DAC6578 DAC7578 |
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