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ADIS16133BMLZ Datasheet(PDF) 11 Page - Analog Devices

Part # ADIS16133BMLZ
Description  짹1200째/sec Precision Angular Rate Sensor
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADIS16133BMLZ Datasheet(HTML) 11 Page - Analog Devices

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ADIS16133
Rev. 0 | Page 11 of 20
DIGITAL PROCESSING CONFIGURATION
Figure 18 provides a block diagram for the sampling and digital
filter stages inside the ADIS16133. Table 15 provides a summary
of digital processing registers for sample rate and filter control.
Table 15. Digital Processing Registers
Register Name
Address
Description
SMPL_PRD
0x1E
Sample rate control
AVG_CNT
0x20
Digital filtering and range control
DEC_RATE
0x22
Decimation rate setting
Internal Sample Rate
The SMPL_PRD register in Table 16 provides a programmable
control for the internal sample rate. Use the following formula
to calculate the decimal number for the code to write into this
register:
SPS
2048
;1
768
,
32
_
=
S
S
f
f
PRD
SMPL
The factory default setting for SMPL_PRD sets the internal
sample rate to a rate of 1024 SPS; the minimum setting for the
SMPL_PRD register is 0x000F, which results in an internal
sample rate of 2048 SPS.
Table 16. SMPL_PRD Bit Descriptions
Bits
Description (Default = 0x001F)
[15:0]
Clock setting bits; sets f
S in Figure 18
Input Clock Configuration
Set SMPL_PRD = 0x0000 (DIN = 0x9F00, then DIN = 0x9E00)
to disable the internal clock and enable CLKIN as a clock input pin.
Digital Filtering
The AVG_CNT register (see Table 17) provides user controls
for the low-pass filter. This filter contains two cascaded averaging
filters that provide a Bartlett window FIR filter response (see
Figure 17). For example, set AVG_CNT[7:0] = 0x04 (DIN =
0xA004) to set each stage to 16 taps. When used with the
default sample rate of 1024 SPS, this establishes a −3 dB
bandwidth of approximately 20 Hz for this filter.
0
–20
–40
–60
–80
–100
–120
–140
0.001
0.01
0.1
1
FREQUENCY (
f/fS)
N = 2
N = 4
N = 16
N = 64
Figure 17. Bartlett Window FIR Filter Frequency Response
(Phase Delay = N Samples)
Table 17. AVG_CNT Bit Descriptions
Bits
Description (Default = 0x0000)
[15:3]
Don’t care
[2:0]
Binary; B variable in Figure 18; maximum setting =
110 (binary) = 6 (decimal)
Averaging/Decimation Filter
The DEC_RATE register (see Table 18) provides user control
for the final filter stage (see Figure 18), which averages and
decimates the output data. For systems that value lower sample
rates, this filter stage provides an opportunity to lower the sample
rate while maintaining optimal bias stability performance. The
−3 dB bandwidth of this filter stage is approximately one half
the output data rate. For example, set DEC_RATE[7:0] = 0x04
(DIN = 0xA204) to reduce the sample rate by a factor of 16.
When the factory default 1024 SPS sample rate is used, this
decimation setting reduces the output data rate to 64 SPS and
the sensor bandwidth to approximately 31 Hz.
Table 18. DEC_RATE Bit Descriptions
Bits
Description (Default = 0x0000)
[15:5]
Don’t care
[4:0]
Binary; D variable in Figure 18; maximum setting =
1000 (binary) = 16 (decimal)
MEMS
GYRO
402Hz
819Hz
CLOCK
fS
CLKIN
÷ND
–3dB BANDWIDTH = 335Hz
B = AVG_CNT[2:0]
NB = 2B
NB = NUMBER OF TAPS PER STAGE
SP
≥ 15
SP = SMPL_PRD
D = DEC_RATE[4:0]
ND = 2D
ND = NUMBER OF TAPS
ND = DATA RATE DIVISOR
fS =
32,768
SP + 1
Figure 18. Sampling and Frequency Response Block Diagram


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