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ADUC7124 Datasheet(PDF) 10 Page - Analog Devices |
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ADUC7124 Datasheet(HTML) 10 Page - Analog Devices |
10 / 96 page ADuC7124 Rev. 0 | Page 10 of 96 SCLOCK (POLARITY = 0) SCLOCK (POLARITY = 1) tSH tSL tSR tSF MOSI MSB BIT 6 TO BIT 1 LSB MISO MSB IN BIT 6 TO BIT 1 LSB IN tDR tDF tDAV tDOSU tDSU tDHD Figure 4. SPI Master Mode Timing (Phase Mode = 0) Table 6. SPI Slave Mode Timing (Phase Mode = 1) Parameter Description Min Typ Max Unit t CS CS 200 to SCLOCK edge ns t SL SCLOCK low pulse width (SPIDIV + 1) × t HCLK ns t SH SCLOCK high pulse width (SPIDIV + 1) × t HCLK ns t DAV Data output valid after SCLOCK edge 25 ns t DSU Data input setup time before SCLOCK edge1 1 × t UCLK ns t DHD Data input hold time after SCLOCK edge1 2 × t UCLK ns t DF Data output fall time 5 12.5 ns t DR Data output rise time 5 12.5 ns t SR SCLOCK rise time 5 12.5 ns t SF SCLOCK fall time 5 12.5 ns t SFS CS 0 high after SCLOCK edge ns 1 t UCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. SCLOCK (POLARITY = 0) CS SCLOCK (POLARITY = 1) tSH tSL tSR tSF tSFS MISO MSB BIT 6 TO BIT 1 LSB MOSI MSB IN BIT 6 TO BIT 1 LSB IN tDHD tDSU tDAV tDR tDF tCS Figure 5. SPI Slave Mode Timing (Phase Mode = 1) |
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