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ADuC7124BCPZ126-RL Datasheet(PDF) 9 Page - Analog Devices |
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ADuC7124BCPZ126-RL Datasheet(HTML) 9 Page - Analog Devices |
9 / 96 page ADuC7124 Rev. 0 | Page 9 of 96 SPI Timing Table 4. SPI Master Mode Timing (Phase Mode = 1) Parameter Description Min Typ Max Unit t SL SCLOCK low pulse width1 (SPIDIV + 1) × t UCLK ns t SH SCLOCK high pulse width1 (SPIDIV + 1) × t UCLK ns t DAV Data output valid after SCLOCK edge 25 ns t DSU Data input setup time before SCLOCK edge1 1 × t UCLK ns t DHD Data input hold time after SCLOCK edge1 2 × t UCLK ns t DF Data output fall time 5 12.5 ns t DR Data output rise time 5 12.5 ns t SR SCLOCK rise time 5 12.5 ns t SF SCLOCK fall time 5 12.5 ns 1 t UCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. SCLOCK (POLARITY = 0) SCLOCK (POLARITY = 1) MOSI MSB BIT 6 TO BIT 1 LSB MISO MSB IN BIT 6 TO BIT 1 LSB IN tSH tSL tSR tSF tDR tDF tDAV tDSU tDHD Figure 3. SPI Master Mode Timing (Phase Mode = 1) Table 5. SPI Master Mode Timing (Phase Mode = 0) Parameter Description Min Typ Max Unit t SL SCLOCK low pulse width1 (SPIDIV + 1) × t UCLK ns t SH SCLOCK high pulse width1 (SPIDIV + 1) × t UCLK ns t DAV Data output valid after SCLOCK edge 25 ns t DOSU Data output setup before SCLOCK edge 75 ns t DSU Data input setup time before SCLOCK edge1 1 × t UCLK ns t DHD Data input hold time after SCLOCK edge1 2 × t UCLK ns t DF Data output fall time 5 12.5 ns t DR Data output rise time 5 12.5 ns t SR SCLOCK rise time 5 12.5 ns t SF SCLOCK fall time 5 12.5 ns 1 t UCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. |
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