tor to GND to limit noise to the internal circuitry. Connect

these bypass capacitors as close as possible to the IC.

Input Undervoltage Lockout

and while PWM is low, DL is driven high and DH is

driven low. This prevents the output of the converter

from rising before a valid PWM signal is applied.

Low-Power Pulse Skipping

The MAX17491 enters into low-power pulse-skipping

mode when SKIP is pulled low. In skip mode, an inherent

automatic switchover to pulse-frequency modulation

(PFM) takes place at light loads. A zero-crossing com-

parator truncates the low-side switch on-time at the

inductor current’s zero crossing. The comparator senses

drops below the zero-crossing comparator threshold

(see the

Electrical Characteristics), the comparator

forces DL low. This mechanism causes the threshold

between pulse-skipping PFM and nonskipping PWM

operation to coincide with the boundary between con-

tinuous and discontinuous inductor-current operation.

The PFM/PWM crossover occurs when the load current

of each phase is equal to 1/2 the peak-to-peak ripple

current, which is a function of the inductor value. For a

battery input range of 7V to 20V, this threshold is rela-

tively constant, with only a minor dependence on the

input voltage due to the typically low duty cycles. The

switching waveforms can appear noisy and asynchro-

nous when light loading activates the pulse-skipping

operation, but this is a normal operating condition that

results in high light-load efficiency.

Applications Information

Power-MOSFET Selection

Most of the following MOSFET guidelines focus on the

challenge of obtaining high load-current capability

when using high-voltage (> 20V) AC adapters. Low-

current applications usually require less attention. The

resistive losses plus the switching losses at both

not vary over a wide range, the minimum power dissi-

pation occurs where the resistive losses equal the

switching losses. Choose a low-side MOSFET that has

a moderate-sized package (i.e., one or two 8-pin SOs,

DPAK, or D2PAK), and is reasonably priced. Ensure

that the DL gate driver can supply sufficient current to

support the gate charge and the current injected into

the parasitic gate-to-drain capacitor caused by the

high-side MOSFET turning on; otherwise, cross-con-

duction problems can occur.

MOSFET Power Dissipation

Worst-case conduction losses occur at the duty factor

case power dissipation due to resistance occurs at the

minimum input voltage:

where

a small high-side MOSFET is desired to reduce switch-

required to stay within package-power dissipation often

limits how small the MOSFETs can be. Again, the opti-

mum occurs when the switching losses equal the con-

do not usually become an issue until the input is greater

than approximately 15V.

Calculating the power dissipation in high-side

it must allow for difficult quantifying factors that influ-

ence the turn-on and turn-off times. These factors

include the internal gate resistance, gate charge,

threshold voltage, source inductance, and PCB layout

characteristics.

The following switching-loss calculation provides only a

very rough estimate and is no substitute for prototype

evaluation, preferably including verification using a

current (5A typ).

PD N

SWITCHING

VI

f

n

Q

I

CV

f

H

IN MAX LOAD SW

TOTAL

GSW

GATE

OSS IN SW

(

)

()

(

)

=

⎛

⎝⎜

⎞

⎠⎟

⎛

⎝⎜

⎞

⎠⎟

+

2

2

PD N

RESISTIVE

V

V

I

R

H

OUT

IN

LOAD

TOTAL

DS ON

(

)

()

=

⎛

⎝⎜

⎞

⎠⎟

⎛

⎝⎜

⎞

⎠⎟

η

2

Single-Phase Synchronous MOSFET Driver

_______________________________________________________________________________________

9