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74LVC2G66GD Datasheet(PDF) 11 Page - NXP Semiconductors |
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74LVC2G66GD Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 26 page 74LVC2G66 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 5 — 16 June 2010 11 of 26 NXP Semiconductors 74LVC2G66 Bilateral switch Σ{(C L +CS(ON)) × VCC 2 × f o} = sum of the outputs. 11.1 Waveforms and test circuit Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 17. Input (nY or nZ) to output (nZ or nY) propagation delays 001aaa541 tPLH tPHL VM VM VM VM nY or nZ input nZ or nY output GND VI VOH VOL Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 18. Enable and disable times 001aaa542 tPLZ tPHZ switch disabled switch enabled switch enabled output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH nE input nY or nZ nY or nZ VI VOL VOH VCC VM VM VX VY VM GND GND tPZL tPZH Table 10. Measurement points Supply voltage Input Output VCC VM VM VX VY 1.65 V to 1.95 V 0.5 × V CC 0.5 × V CC VOL + 0.15 V VOH − 0.15 V 2.3 V to 2.7 V 0.5 × V CC 0.5 × V CC VOL + 0.15 V VOH − 0.15 V 2.7V 1.5V 1.5V VOL + 0.3 V VOH − 0.3 V 3.0Vto 3.6V 1.5V 1.5V VOL + 0.3 V VOH − 0.3 V 4.5 V to 5.5 V 0.5 × V CC 0.5 × V CC VOL + 0.3 V VOH − 0.3 V |
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