LPC1102 datasheet(10/38 Pages) NXP

Part #	LPC1102

Description	32-bit ARM Cortex-M0 microcontroller; 32 kB flash and 8 kB SRAM

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Manufacturer	NXP [NXP Semiconductors]

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LPC1102

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 00 — 23 June 2010

10 of 38

NXP Semiconductors

LPC1102

32-bit ARM Cortex-M0 microcontroller

• Measurement range 0 V to VDD.

• 10-bit conversion time ≥ 2.44 μs.

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition of input pin or timer match signal.

• Individual result registers for each ADC channel to reduce interrupt overhead.

7.11 General purpose external event counter/timers

The LPC1102 includes two 32-bit counter/timers and two 16-bit counter/timers. The

counter/timer is designed to count cycles of the system derived clock. It can optionally

generate interrupts or perform other actions at specified timer values, based on four

match registers. Each counter/timer also includes one capture input to trap the timer value

when an input signal transitions, optionally generating an interrupt.

7.11.1 Features

• A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.

• Counter or timer operation.

• One capture channel that can take a snapshot of the timer value when an input signal

transitions. A capture event may also generate an interrupt.

• Four match registers per timer that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Up to four external outputs corresponding to match registers, with the following

capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

7.12 System tick timer

The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).

7.13 Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a selectable time

period.

7.13.1 Features

• Internally resets chip if not periodically reloaded.

• Debug mode.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

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