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UR5596-SH2-R Datasheet(PDF) 7 Page - Unisonic Technologies

Part # UR5596-SH2-R
Description  DDR TERMINATION REGULATOR
Download  12 Pages
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Manufacturer  UTC [Unisonic Technologies]
Direct Link  http://www.utc-ic.com
Logo UTC - Unisonic Technologies

UR5596-SH2-R Datasheet(HTML) 7 Page - Unisonic Technologies

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UR5596
CMOS IC
UNISONICTECHNOLOGIESCO.,LTD
7 of 12
www.unisonic.com.tw
QW-R502-045,C
TYPICAL APPLICATION CIRCUITS
Following demonstrate several different application circuits to illustrate some of the options that are possible in
configuring the UTC UR5596. The individual circuit performance can be found in the Typical Performance
Characteristics that curve graphs illustrate how the maximum output current is affected by changes in AVIN and PVIN.
STUB-SERIES TERMINATED LOGIC(SSTL) TERMINATION SCHEME
SSTL was created to improve signal integrity of the data transmission across the memory bus. This termination
scheme is essential to prevent data error from signal reflections while transmitting at high frequencies encountered
with DDR-SDRAM. Class II single parallel termination(SSTL-2) is the most popular termination form. It involves one
RS series resistor from the chipset to the memory and one RT termination resistor (refer to Figure 1). RS and RT are
changeable to meet the current requirement from UR5596, the recommended values both RS and RT are 25Ω.
Figure 1. SSTL-Termination Scheme
FOR SSTL-2 APPLICATIONS
For the majority of applications that implement the SSTL- 2 termination scheme, it is recommended to connect all
the input rails to the 2.5V rail as Figure 2. This provides an optimal trade-off between power dissipation and
component count and selection.
+
+
+
VTT
VDDQ
VSENSE
VREF
GND
SHDN
AVIN
PVIN
CIN
SHDN
VDDQ=2.5V
VDD=2.5V
COUT
CREF
VREF=1.25V
VTT=1.25V
UTC UR5596
Figure 2. Recommended SSTL-2 Implementation


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