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SST25VF064C-80-4I-Q2CE Datasheet(PDF) 10 Page - Silicon Storage Technology, Inc |
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SST25VF064C-80-4I-Q2CE Datasheet(HTML) 10 Page - Silicon Storage Technology, Inc |
10 / 31 page 10 Data Sheet 64 Mbit SPI Serial Dual I/O Flash SST25VF064C ©2010 Silicon Storage Technology, Inc. S71392-04-000 04/10 Read (33 MHz) The Read instruction, 03H, supports up to 33 MHz Read. The device outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high tran- sition on CE#. The internal address pointer will automati- cally increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space. For exam- ple, once the data from address location 7FFFFFH has been read, the next output will be from address location 000000H. The Read instruction is initiated by executing an 8-bit com- mand, 03H, followed by address bits A23-A0. CE# must remain active low for the duration of the Read cycle. See Figure 6 for the Read sequence. FIGURE 6: Read Sequence High-Speed Read (80 MHz) The High-Speed Read instruction supporting up to 80 MHz Read is initiated by executing an 8-bit command, 0BH, fol- lowed by address bits A23-A0 and a dummy byte. CE# must remain active low for the duration of the High-Speed Read cycle. See Figure 7 for the High-Speed Read sequence. Following a dummy cycle, the High-Speed Read instruction outputs the data starting from the specified address loca- tion. The data output stream is continuous through all addresses until terminated by a low to high transition on CE#. The internal address pointer will automatically incre- ment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap- around) of the address space. For example, once the data from address location 7FFFFFH is read, the next output is from address location 000000H. 5. 32KByte Block Erase addresses: use AMS-A15, remaining addresses are don’t care but must be set either at VIL or VIH. 6. 64KByte Block Erase addresses: use AMS-A16, remaining addresses are don’t care but must be set either at VIL or VIH. 7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#. 8. Manufacturer’s ID is read with A0 = 0, and Device ID is read with A0 = 1. All other address bits are 00H. The Manufacturer’s ID and device ID output stream is continuous until terminated by a low-to-high transition on CE#. 9. Requires a prior WREN command. 1392 F06.0 CE# SO SI SCK ADD. 01 2 3 4 5 6 7 8 ADD. ADD. 03 HIGH IMPEDANCE 15 16 23 24 31 32 39 40 70 47 48 55 56 63 64 N+2 N+3 N+4 N N+1 DOUT MSB MSB MSB MODE 0 MODE 3 DOUT DOUT DOUT DOUT |
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