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SST49LF030A-33-4C-WHE Datasheet(PDF) 10 Page - Silicon Storage Technology, Inc

Part # SST49LF030A-33-4C-WHE
Description  3 Mbit LPC Flash
Download  49 Pages
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Manufacturer  SST [Silicon Storage Technology, Inc]
Direct Link  http://www.sst.com/
Logo SST - Silicon Storage Technology, Inc

SST49LF030A-33-4C-WHE Datasheet(HTML) 10 Page - Silicon Storage Technology, Inc

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EOL Product Data Sheet
3 Mbit LPC Flash
SST49LF030A
©2005 Silicon Storage Technology, Inc.
S71234-03-EOL
5/06
MODE SELECTION
The SST49LF030A flash memory devices can operate in
two distinct interface modes: the LPC mode and the Parallel
Programming (PP) mode. The mode pin is used to set the
interface mode selection. If the mode pin is set to logic High,
the device is in PP mode. If the mode pin is set Low, the
device is in the LPC mode. The mode selection pin must be
configured prior to device operation. The mode pin is inter-
nally pulled down if the pin is left unconnected. In LPC
mode, the device is configured to its host using standard
LPC interface protocol. Communication between Host and
the SST49LF030A occurs via the 4-bit I/O communication
signals, LAD [3:0] and LFRAME#. In PP mode, the device
is programmed via an 11-bit address and an 8-bit data I/O
parallel signals. The address inputs are multiplexed in row
and column selected by control signal R/C# pin. The row
addresses are mapped to the lower internal addresses
(A10-0), and the column addresses are mapped to the
higher internal addresses (AMS-11). See Figure 4, the
Device Memory Map, for address assignments.
LPC MODE
Device Operation
The LPC mode uses a 5-signal communication interface, a
4-bit address/data bus, LAD[3:0], and a control line,
LFRAME#, to control operations of the SST49LF030A.
Cycle type operations such as Memory Read and Memory
Write are defined in Intel Low Pin Count Interface Specifi-
cation, Revision 1.0. JEDEC Standard SDP (Software
Data
Protection)
Program
and
Erase
commands
sequences are incorporated into the standard LPC mem-
ory cycles. See Figures 7 through 12 for command
sequences.
LPC signals are transmitted via the 4-bit Address/Data bus
(LAD[3:0]), and follow a particular sequence, depending on
whether they are Read or Write operations. LPC memory
Read and Write cycle is defined in Tables 5 and 6.
Both LPC Read and Write operations start in a similar way
as shown in Figures 5 and 6. The host (which is the term
used here to describe the device driving the memory)
asserts LFRAME# for two or more clocks and drives a start
value on the LAD[3:0] bus.
At the beginning of an operation, the host may hold the
LFRAME# active for several clock cycles, and even change
the Start value. The LAD[3:0] bus is latched every rising
edge of the clock. On the cycle in which LFRAME# goes
inactive, the last latched value is taken as the Start value.
CE# must be asserted one cycle before the start cycle to
select the SST49LF030A for Read and Write operations.
Once the SST49LF030A identify the operation as valid (a
start value of all zeros), it next expects a nibble that indi-
cates whether this is a memory Read or Write cycle. Once
this is received, the device is now ready for the Address
cycles. The LPC protocol supports a 32-bit address phase.
The SST49LF030A encode ID and register space access
in the address field. See Table 3 for address bits definition.
For Write operation the Data cycle will follow the Address
cycle, and for Read operation TAR and SYNC cycles occur
between the Address and Data cycles. At the end of every
operation, the control of the bus must be returned to the
host by a 2-clock TAR cycle.
CE#
The CE# pin, enables and disables the SST49LF030A,
controlling read and write access of the device. To enable
the SST49LF030A, the CE# pin must be driven low one
clock cycle prior to LFRAME# being driven low. The device
will enter standby mode when internal Write operations are
completed and CE# is high.
LFRAME#
The LFRAME# signifies the start of a (frame) bus cycle or
the termination of an undesired cycle. Asserting LFRAME#
for two or more clock cycle and driving a valid START value
on LAD[3:0] will initiate device operation. The device will
enter standby mode when internal operations are com-
pleted and LFRAME# is high.
TABLE
3: Address bits definition1
1. For the SST49LF030A, operations beyond the 3 Mbit boundary (below 20000H) are not valid (see Device Memory Map).
A31: A242
2. For SST49LF030A, the top 16MByte address range FFFF FFFFH to FF00 0000H and the bottom 128 KByte memory access
address 000F FFFFH to 000E 0000H are decoded.
A23
A22
A21: A19
A18:A0
1111 1111b or 0000 0000b
ID[3]3
3. See Table 7 for multiple device selection configuration.
1 = Memory Access
0 = Register access
ID[2:0]3
Device Memory address
T3.0 1234


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