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AT32UC3A4256-C1UR Datasheet(PDF) 5 Page - ATMEL Corporation |
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AT32UC3A4256-C1UR Datasheet(HTML) 5 Page - ATMEL Corporation |
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5 / 90 page  5 32072C–AVR32–2010/03 AT32UC3A3/A4 2.1 Processor and Architecture 2.1.1 AVR32 UC CPU • 32-bit load/store AVR32A RISC architecture – 15 general-purpose 32-bit registers – 32-bit Stack Pointer, Program Counter and Link Register reside in register file – Fully orthogonal instruction set – Privileged and unprivileged modes enabling efficient and secure Operating Systems – Innovative instruction set together with variable instruction length ensuring industry leading code density – DSP extension with saturating arithmetic, and a wide variety of multiply instructions • Three stage pipeline allows one instruction per clock cycle for most instructions – Byte, halfword, word and double word memory access – Multiple interrupt priority levels • MPU allows for operating systems with memory protection 2.1.2 Debug and Test System • IEEE1149.1 compliant JTAG and boundary scan • Direct memory access and programming capabilities through JTAG interface • Extensive On-Chip Debug features in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+ – Low-cost NanoTrace supported • Auxiliary port for high-speed trace information • Hardware support for six Program and two data breakpoints • Unlimited number of software breakpoints supported • Advanced Program, Data, Ownership and Watchpoint trace supported 2.1.3 Peripheral DMA Controller • Transfers from/to peripheral to/from any memory space without intervention of the processor • Next Pointer Support, forbids strong real-time constraints on buffer management • Eight channels and 24 Handshake interfaces – Two for each USART – Two for each Serial Synchronous Controller (SSC) – Two for each Serial Peripheral Interface (SPI) –One for ADC – Four for each TWI Interface – Two for each Audio Bit Stream DAC 2.1.4 Bus System • High Speed Bus (HSB) matrix with 7 Masters and 10 Slaves handled – Handles Requests from • Masters: the CPU (Instruction and Data Fetch), PDCA, CPU SAB, USBB, DMACA • Slaves: the internal Flash, internal SRAM, Peripheral Bus A, Peripheral Bus B, External Bus Interface (EBI), Advanced Encrytion Standard (AES) – Round-Robin Arbitration (three modes supported: no default master, last accessed default master, fixed default master) – Burst breaking with Slot Cycle Limit – One address decoder provided per master • Peripheral Bus A able to run on at divided bus speeds compared to the High Speed Bus |
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