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ISL6324ACRZ Datasheet(PDF) 9 Page - Intersil Corporation |
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ISL6324ACRZ Datasheet(HTML) 9 Page - Intersil Corporation |
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9 / 39 page  9 FN6880.0 March 23, 2009 Functional Pin Description VID1/SEL This pin selects SVI or PVI mode operation based on the state of the pin prior to enabling the ISL6324A. If the pin is LO prior to enable, the ISL6324A is in SVI mode and the dual purpose pins [VID0/VFIXEN, VID2/SVC, VID3/SVD] use their SVI mode related functions. If the pin held HI prior to enable, the ISL6324A is in PVI mode and dual purpose pins use their VIDx related functions to decode the correct DAC code. VID0/VFIXEN If VID1 is LO prior to enable [SVI Mode], the pin is functions as the VFIXEN selection input from the AMD processor for determining SVI mode versus VFIX mode of operation. If VID1 is HI prior to enable [PVI Mode], the pin is used as DAC input VID0. This pin has an internal 30µA pull-down current applied to it at all times. VID2/SVD If VID1 is LO prior to enable [SVI Mode], this pin is the serial VID data bi-directional signal to and from the master device on AMD processor. If VID1 is HI prior to enable [PVI Mode], this pin is used to decode the programmed DAC code for the processor. In PVI mode, this pin has an internal 30µA pull-down current applied to it. There is no pull-down current in SVI mode. VID3/SVC If VID1 is LO prior to enable [SVI Mode], this pin is the serial VID clock input from the AMD processor. If VID1 is HI prior to enable [PVI Mode], the ISL6324A is in PVI mode and this pin is used to decode the programmed DAC code for the processor. In PVI mode, this pin has an internal 30µA pull-down current applied to it. There is no pull-down current in SVI mode. VID4 This pin is active only when the ISL6324A is in PVI mode. When VID1 is HI prior to enable, the ISL6324A decodes the programmed DAC voltage required by the AMD processor. This pin has an internal 30µA pull-down current applied to it at all times. VID5 This pin is active only when the ISL6324A is in PVI mode. When VID1 is HI prior to enable, the ISL6324A decodes the programmed DAC voltage required by the AMD processor. This pin has an internal 30µA pull-down current applied to it at all times. VCC VCC is the bias supply for the ICs small-signal circuitry. Connect this pin to a +5V supply and decouple using a quality 0.1µF ceramic capacitor. PVCC1_2 The power supply pin for the multi-phase internal MOSFET drivers. Connect this pin to any voltage from +5V to +12V depending on the desired MOSFET gate-drive level. Decouple this pin with a quality 1.0µF ceramic capacitor. PVCC_NB The power supply pin for the internal MOSFET driver for the Northbridge controller. Connect this pin to any voltage from +5V to +12V depending on the desired MOSFET gate-drive level. Decouple this pin with a quality 1.0µF ceramic capacitor. GND GND is the bias and reference ground for the IC. The GND connection for the ISL6324A is through the thermal pad on the bottom of the package. EN This pin is a threshold-sensitive (approximately 0.85V) system enable input for the controller. Held low, this pin disables both CORE and NB controller operation. Pulled high, the pin enables both controllers for operation. When the EN pin is pulled high, the ISL6324A will be placed in either SVI or PVI mode. The mode is determined by the latched value of VID1 on the rising edge of the EN signal. A third function of this pin is to provide driver bias monitor for external drivers. A resistor divider with the center tap connected to this pin from the drive bias supply prevents enabling the controller before insufficient bias is provided to external driver. The resistors should be selected such that when the POR-trip point of the external driver is reached, the voltage at this pin meets the above mentioned threshold level. FS A resistor, placed from FS to Ground or from FS to VCC, sets the switching frequency of both controllers. Refer to Equation 1 for proper resistor calculation. With the resistor tied from FS to Ground, Droop is enabled. With the resistor tied from FS to VCC, Droop is disabled. VSEN and RGND VSEN and RGND are inputs to the core voltage regulator (VR) controller precision differential remote-sense amplifier and should be connected to the sense pins of the remote processor core(s), VDDFB[H,L]. FB and COMP These pins are the internal error amplifier inverting input and output respectively of the core VR controller. FB, VSEN and COMP are tied together through external R-C networks to compensate the regulator. APA Adaptive Phase Alignment (APA) pin for setting trip level and adjusting time constant. A 100µA current flows into the APA pin and by tying a resistor from this pin to COMP the trip level for the Adaptive Phase Alignment circuitry can be set. (EQ. 1) R T 10 10.61 1.035 f s () log – [] = ISL6324A ISL6324A |
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