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ISL6112INZA Datasheet(PDF) 11 Page - Intersil Corporation |
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ISL6112INZA Datasheet(HTML) 11 Page - Intersil Corporation |
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11 / 31 page  11 FN6456.0 September 28, 2007 ISL6112 Bias, Power-On Reset and Power Cycling The ISL6112 utilizes VSTBY as the only supply source. VSTBY is required for proper operation of the ISL6112’s SMBus and registers and must be applied at all times. A Power-On Reset (POR) cycle is initiated after VSTBY rises above its UVLO threshold and remains satisfied for 250µs. All internal registers are cleared after POR. If VSTBY is recycled, the ISL6112 enters a new power-on-reset cycle. VSTBY must be the first supply voltage applied followed by the MAIN supply inputs of 12VIN and 3VIN. The SMBus is ready for access at the end of the POR cycle (250µs after VSTBY is valid). During tPOR, all outputs remain off. Enabling the VAUX Outputs Upon asserting an AUXEN input, the related internal power switch turns on connecting the nominally 3.3V VSTBY supply to its VAUX load. The turn-on is slew rate limited and invokes the ICs current regulation feature so as to not droop the supply due to in-rush current load. Figure 2 illustrates the VAUX turn-on performance into a 10 Ω, 100µF load. Standby Mode Standby mode is entered when one or more of the MAIN supply inputs (12VIN and/or 3VIN) is absent, below its respective UVLO threshold or OFF. The ISL6112 also has 3.3V auxiliary outputs (VAUXA and VAUXB), satisfying an optional PCI Express requirement. These outputs are fed from the VSTBY input pins, they are independent of the MAIN outputs and are controlled by the AUXEN input pins or via their respective bits in the control registers. Should the MAIN supply inputs fall below their respective UVLO thresholds, VAUX will still function as long as VSTBY is compliant. Prior to standby mode, ONA and ONB (or the control registers' MAINA and MAINB bits) inputs must be deasserted or else the ISL6112 will assert its FAULT outputs. If an undervoltage condition on either of the MAIN supply inputs is detected, the INT will also assert if interrupts are enabled. Enabling the MAIN GATE outputs When a slot's MAIN supplies are off, the 12VGATE pin is held high with an internal pull-up to the 12VIN voltage. Similarly, the 3VGATE pin is internally held low to GND. When the MAIN supplies of the ISL6112 are enabled by asserting ON, the related 3VGATE and 12VGATE pins are each connected to a constant current supply. For the 3VGATE pin, this is nominally a 25µA current source and for the 12VGATE pin, this is nominally a -25µA current sink. The 3VGATE will be charged up to the 12VIN voltage whereas the 12GATE will be pulled down to GND for maximum enhancement of the N-Channel and P-Channel FETs, respectively. Estimating In-Rush Current and VOUT Slew Rate at Start-up The expected in-rush current can be estimated by using Equation 1: with 25µA being the GATE pin charge current, CLOAD is the load capacitance, and CGATE is the total GATE capacitance including CISS of the external MOSFET and any external capacitance connected from the GATE output pin to the GATE reference, GND or source. An estimate for the output slew rate of 3.3V outputs and 12V outputs where there is little or no external 12VGATE output capacitors, can be had from Equation 2: DISABLING SMI WHEN HPI CONTROL IS USED DISABLING HPI WHEN SMI CONTROL IS USED SCL SDA INT# A2 A1 A0 100k 100k 100k VSTBY INT FORON#_A FORON#_B AUXENA AUXENB ONA ONB 100k 100k VSTBY 9 28 45 42 44 43 FIGURE 1. I/O CONFIGURATION FOR DISABLING HPI/SMI CONTROL VAUX IAUX AUXEN VAUX IAUX AUXEN FIGURE 2. VAUX TURN-ON RLOAD = 10Ω, CLOAD = 100µF (EQ. 1) I IN RUSH – NOMINALLY 25 μA C LOAD C GATE -------------------- ⎝⎠ ⎜⎟ ⎛⎞ = (EQ. 2) dv/dt VOUT NOMINALLY I LIM C LOAD -------------------- = ISL6112 |
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