9

FN6535.0

March 26, 2008

Pin Descriptions

SYMBOL

QFN PIN #(s)

DESCRIPTION

4

Analog input. Red channel. DC couple or AC couple through 0.1µF.

7

Analog input. Green channel. DC couple or AC couple through 0.1µF.

11

Analog input. Blue channel. DC couple or AC couple through 0.1µF.

8

18

Digital input, 5V tolerant, 240mV hysteresis, 1.2k

Ω impedance to GND. Connect to HSYNC signal through a

680

Ω series resistor.

27

Digital input, 5V tolerant, 500mV hysteresis. Connect to VSYNC signal.

13

Analog input. Red channel. DC couple or AC couple through 0.1µF.

14

Analog input. Green channel. DC couple or AC couple through 0.1µF.

16

Analog input. Blue channel. DC couple or AC couple through 0.1µF.

15

25

Digital input, 5V tolerant. When high, inverts the pixel sampling phase by 180°. Tie to GND if unused.

RESET

28

Digital input, 5V tolerant, active low, 70k

Ω pull-up to V

22

Analog input. Connect to external 24.5MHz to 27MHz crystal and load capacitor (see “Electrical

around 0.5V.

24

Analog output. Connect to external 24.5MHz to 27MHz crystal and load capacitor (see “Electrical

around 0.5V.

SADDR

29

Digital input, 5V tolerant. Address = 0x4C when tied low. Address = 0x4D when tied high.

SCL

31

Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface.

SDA

30

Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface.

R7 thru R0

59 thru 66

3.3V digital output. Red channel, primary pixel data. 56k pull-down when three-stated.

G7 thru G0

46 thru 52, 54

3.3V digital output. Green channel, primary pixel data. 56k pull-down when three-stated.

B7 thru B0

36 thru 43

3.3V digital output. Blue channel, primary pixel data. 56k pull-down when three-stated.

DATACLK

67

3.3V digital output. Data clock output. Equal to pixel clock rate.

DATACLK

68

3.3V digital output. Inverse of DATACLK.

70

3.3V digital output. HSYNC output aligned with pixel data. Use this output to frame the digital output data.

This output is always purely horizontal sync (without any composite sync signals).

71

3.3V digital output. Buffered HSYNC (or SOG or CSYNC) output. This is typically used for measuring HSYNC

72

3.3V digital output. Buffered VSYNC output. For composite sync signals, this output will be asserted for the

duration of the disruption of the normal HSYNC pattern. This is typically used for measuring VSYNC period.

3, 6, 10, 12, 19

35, 44, 45, 56,

58, 69

21

GND

PAD, 23, 34

Ground return.

1, 5, 9

Internal power for the ADC’s analog. Connect to a 1.8V supply and bypass to GND with 0.1µF.

17

Internal power for the ADC’s digital logic. Connect to a 1.8V supply and bypass to GND with 0.1µF.

32, 57

Internal power for core logic. Connect to a 1.8V supply and bypass each pin to GND with 0.1µF.

26

Internal power for the PLL’s digital logic. Connect to a 1.8V supply and bypass to GND with 0.1µF.

NC

2, 20, 33, 53, 55

Reserved. Do not connect anything to these pins.

ISL98002