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ISL6263AIRZ Datasheet(PDF) 11 Page - Intersil Corporation |
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ISL6263AIRZ Datasheet(HTML) 11 Page - Intersil Corporation |
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11 / 19 page  11 FN9284.3 July 8, 2010 Static Regulation The VCCGFX output voltage will be regulated to the value set by the VID inputs per Table 2. A true differential amplifier connected to the VSEN and RTN pins implements processor socket Kelvin sensing for precise core voltage regulation at the GPU voltage sense points. As the load current increases from zero, the VCCGFX output voltage will droop from the VID set-point by an amount proportional to the IMVP-6+ load line. The ISL6263A can accommodate DCR current sensing or discrete resistor current sensing. The DCR current sensing uses the intrinsic series resistance of the output inductor as shown in the application circuit of Figure 2. The discrete resistor current sensing uses a shunt connected in series with the output inductor as shown in the application circuit of Figure 3. In both cases the signal is fed to the non-inverting input of the DROOP amplifier at the VSUM pin, where it is measured differentially with respect to the output voltage of the converter at the VO pin and amplifier. The voltage at the DROOP pin minus the output voltage measured at the VO pin, is proportional to the total inductor current. This information is used exclusively to achieve the IMVP-6+ load line as well as the overcurrent protection. It is important to note that this current measurement should not be confused with the synthetic current ripple information created within the R3 modulator. When using inductor DCR current sensing, an NTC element is used to compensate the positive temperature coefficient of the copper winding thus maintaining the load-line accuracy. Processor Socket Kelvin Voltage Sensing The remote voltage sense input pins VSEN and RTN of the ISL6263A are to be terminated at the die of the GPU through connections that mate at the processor socket. (The signal names are VCC_SENSE and VSS_SENSE respectively). Kelvin sensing allows the voltage regulator to tightly control the processor voltage at the die, compensating for various resistive voltage drops in the power delivery path. Since the voltage feedback is sensed at the processor die, removing the GPU will open the voltage feedback path of the regulator, causing the output voltage to rise towards VIN. The ISL6263A will shut down when the voltage between the VO and VSS pins exceeds the severe overvoltage protection threshold VOVPS of 1.55V. To prevent this issue from occurring, it is recommended to install resistors ROPN1 and ROPN2 as shown in Figure 5. These resistors provide voltage feedback from the regulator local output in the absence of the GPU. These resistors should be in the range of 20 Ω to 100Ω. High Efficiency Diode Emulation Mode The ISL6263A operates in continuous-conduction-mode (CCM) during heavy load for minimum conduction loss by forcing the low-side MOSFET to operate as a synchronous rectifier. An improvement in light-load efficiency is achieved by allowing the converter to operate in diode-emulation mode (DEM) where the low-side MOSFET behaves as a smart-diode, forcing the device to block negative inductor current flow. Positive-going inductor current flows from either the source of the high-side MOSFET, or the drain of the low-side MOSFET. Negative-going inductor current flows into the source of the high-side MOSFET, or into the drain of the low-side MOSFET. When the low-side MOSFET conducts positive inductor current, the phase voltage will be negative with respect to the VSS pin. Conversely, when the low-side MOSFET conducts negative inductor current, the phase voltage will be positive with respect to the VSS pin. Negative inductor current occurs when the output DC load current is less than ½ the inductor ripple current. Sinking negative inductor current through the low-side MOSFET lowers efficiency through unnecessary conduction losses. Efficiency can be further improved with a reduction of unnecessary switching losses by reducing the PWM frequency. The PWM frequency can be configured to automatically make a step-reduction upon entering DEM by forcing a step-increase of the window voltage VW. The window voltage can be configured to increase approximately 30%, 50%, or not at all. The characteristic PWM frequency reduction, coincident with decreasing load, is accelerated by the step-increase of the window voltage. An audio filter can be enabled that briefly turns on the low-side MOSFET gate driver LGATE approximately every 35µs. The converter will enter DEM after detecting three consecutive PWM pulses with negative inductor current. The negative inductor current is detected during the time that the high-side MOSFET gate driver output UGATE is low, with the exception of a brief blanking period. The voltage between the PHASE pin and VSS pin is monitored by a comparator that latches upon detection of the positive phase voltage. The converter will return to CCM after detecting three consecutive PWM pulses with positive inductor current. The inductor current is considered positive if the phase comparator has not been latched while UGATE is low. VR_ON VSOFT/VCCGFX PGOOD 13 SWITCHING CYCLES ~100¬µ 90% FIGURE 4. ISL6263A START-UP TIMING ISL6263A |
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