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ISL88706IB844Z Datasheet(PDF) 7 Page - Intersil Corporation

Part # ISL88706IB844Z
Description  uP Supervisor with Watchdog Timer, Power-Fail Comparator, Manual Reset and Adjustable Power-On Reset
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL88706IB844Z Datasheet(HTML) 7 Page - Intersil Corporation

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7
FN8092.5
January 12, 2009
Low Voltage Monitoring
These devices monitor both the voltage level of VDD and an
auxiliary voltage on PFI.
When IC is initially biased reset is asserted until the VDD
voltage is greater than the specific IC fixed-voltage trip point
for the tPOR duration of 200ms. At any subsequent time that
VDD does not exceed its voltage threshold, reset is once
again asserted, i.e. RST is high and RST is low (see
Figure 1).
.
Power Failure Monitor
These devices also have a Power-Failure Monitor that helps
to monitor an additional critical voltage on the Power-Fail
Input (PFI) pin. For example, the PFI pin could be used to
provide an early power-fail warning, detect a low-battery
condition, presence detection or simply monitor a power
supply other than +5V. The 1.25V threshold detector can be
adjusted using an external resistor divider network to provide
custom voltage monitoring of voltages greater than 1.25V,
according to Equation 1 (see Figure 2).
PFO goes low whenever PFI is less than the 1.25V (or
user-set) threshold voltage.
.
If using a voltage divider on the PFI input to critique an
external voltage and intending to use the MR input to initiate
resets then avoid having the PFI voltage less than PFI Vth
+2.2V as unintended PFO transition may occur when MR is
transitioning high.
Adjusting tPOR
On the ISL88707 and ISL88708, users can adjust the
Power-On Reset time-out delay (tPOR) to many times the
nominal tPOR of 200ms. To do this, connect a capacitor
between CPOR and ground (see Figure 3). For example,
connecting a 50pF capacitor to CPOR will increase tPOR from
200ms to ~1.4s. Care should be taken in PCB layout and
capacitor placement in order to reduce stray capacitance as
much as possible, which contributes to tPOR error.
FIGURE 1. POWER-SUPPLY MONITORING TIMING DIAGRAM (WDI TRI-STATED)
VDD
MR
RST
tPOR
VTH1
1V
tPOR
tPOR
>tMR
tRPD
RST
PFI V
TH
1.25
R
1
R
2
+
R
2
---------------------
⎝⎠
⎜⎟
⎛⎞
=
(EQ. 1)
FIGURE 2. CUSTOM VTH WITH RESISTOR DIVIDER ON PFI
VIN
R1
R2
PFI
ISL8870x
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813


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