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ISL8118IRZ Datasheet(PDF) 10 Page - Intersil Corporation |
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ISL8118IRZ Datasheet(HTML) 10 Page - Intersil Corporation |
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10 / 20 page  10 FN6325.0 August 1, 2006 EXDRV (Pin 15, External Linear Regulator Drive) This pin allows the use of an external pass element to power the IC for input voltages above 5.0V. It should be connected to GND when using an external 5V supply or the internal linear regulator. When using the external linear regulator option, this pin should be connected to the gate of a PMOS pass element, a pull-up resistor must be connected between the PMOS device’s gate and source for proper operation. PVCC (Pin 16, Driver Bias Voltage) This pin is the output of the internal series linear regulator. It also provides the bias for both bottom side and top side MOSFET drivers. The maximum voltage differential between PVCC and PGND is 6V. Its recommended operational voltage range is 2.9V to 5.6V. At minimum a 10µF capacitor is required for decoupling PVCC to PGND. For proper operation the PVCC capacitor must be within 150 mils of the PVCC and the PGND pins and must be connected to these pins with dedicated traces. BGATE (Pin 17) This pin provides the drive for the bottom side MOSFET and should be connected to its gate. PGND (Pin 18, Power Ground) This pin connects to the bottom side MOSFET's source and provides the ground return path for the lower MOSFET driver and internal power circuitries. In addition, PGND is the return path for the bottom side MOSFET’s rDS(ON) current sensing circuit. LX (Pin 19) This pin connects to the source of the top side MOSFET and the drain of the bottom side MOSFET. This pin represents the return path for the top side gate driver. During normal switching, this pin is used for top side and bottom side current sensing. TGATE (Pin 20) This pin provides the drive for the top side MOSFET and should be connected to its gate. BOOT (Pin 21) This pin provides the bootstrap bias for the top side driver. The absolute maximum voltage differential between BOOT and LX is 6.0V (including the voltage added due to the overcharging of the bootstrap capacitor); its operational voltage range is 2.5V to 5.6V with respect to LX. It is recommended that a 2.2 Ω resistor be placed in series with the bootstrap diode to prevent over charging of the BOOT capacitor during normal operation. TSOC (Pin 22) The top side sourcing current limit is set by connecting this pin with a resistor and capacitor to the drain of the top side MOSEFT. A 100µA current source develops a voltage across the resistor which is then compared with the voltage developed across the top side MOSFET. An initial ~120ns blanking period is used to eliminate sampling error due to the switching noise before the current is measured. BSOC (Pin 23) The bottom side source and sinking current limit is set by placing a resistor (RBSOC) and capacitor between this pin and PGND. A 100µA current source develops a voltage across RBSOC which is then compared with the voltage developed across the bottom side MOSFET when on. The sinking current limit is set at 1x of the nominal sourcing limit in ISL8118. An initial ~120ns blanking period is used to eliminate the sampling error due to switching noise before the current is measured. FSET (Pin 24) This pin provides oscillator switching frequency adjustment by placing a resistor (RFSET) from this pin to GND. COMP (Pin 25) This pin is the error amplifier output. It should be connected to the FB pin through the desired compensation network. FB (Pin 26) This pin is the inverting input of the error amplifier and has a maximum usable voltage of VCC-1.8V. When using the internal differential remote sense functionality, this pin should be connected to VDIFF by a standard feedback network. In the event the remote sense buffer is disabled, the VDIFF pin should be connected to VOUT by a resistor divider along with FB’s compensation network. GND (Pin 27, Analog Ground) Signal ground for the IC. All voltage levels are measured with respect to this pin. This pin should not be left floating. VDIFF (Pin 28) This pin is the output of the differential remote sense instrumentation amplifier. It is connected internally to the OV/UV/PGOOD comparators. The VDIFF pin should be connected to the FB pin by a standard feedback network. In the event of the remote sense buffer is disabled, the VDIFF pin should be connected to VOUT by a resistor divider along with FB’s compensation network. An RC filter should be used if VDIFF is to be connected directly to FB instead of to VOUT through a separate resistor divider network. GND (Bottom Side Pad, Analog Ground) Signal ground for the IC. All voltage levels are measured with respect to this pin. This pin should not be left floating. ISL8118 |
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