10

FN7385.6

March 2, 2009

Disable/Power-Down

The EL5152 and EL5253 can be disabled with their output

placed in a high impedance state. The turn off time is about

330ns and the turn on time is about 130ns. When disabled,

the amplifier's supply current is reduced to 17µA typically;

essentially eliminating power consumption. The amplifier's

power down is controlled by standard TTL or CMOS signal

levels at the ENABLE pin. The applied logic signal is relative

amplifier. The amplifier is disabled when the signal at

Output Drive Capability

The EL5152 and EL5153 families do not have internal short

circuit protection circuitry. Typically, short circuit currents as

high as 95mA and 70mA can be expected and naturally, if

the output is shorted indefinitely the part can easily be

damaged from overheating, or excessive current density

may eventually compromise metal integrity. Maximum

reliability is maintained if the output current is always held

below ±40mA. This limit is set and limited by the design of

the internal metal interconnect. Note that in transient

applications, the part is extremely robust.

Power Dissipation

With the high output drive capability of the EL5152 and

EL5153 families, it is possible to exceed the +125°C

absolute maximum junction temperature under certain load

current conditions. Therefore, it is important to calculate the

maximum junction temperature for an application to

determine if load conditions or package types need to be

modified to assure operation of the amplifier in a safe

operating area.

The maximum power dissipation allowed in a package is

determined according to Equation 2:

Where:

The maximum power dissipation actually produced by an IC

is the total quiescent supply current times the total power

supply voltage, plus the power in the IC due to the load, or:

For sourcing:

For sinking:

Where:

N = number of amplifiers (Max = 2)

overheat.

Power Supply Bypassing Printed Circuit Board

Layout

As with any high frequency device, a good printed circuit

board layout is necessary for optimum performance. Lead

lengths should be as short as possible. The power supply

pin must be well bypassed to reduce the risk of oscillation.

connected to the ground plane, a single 4.7µF tantalum

to GND will suffice. This same capacitor combination should

be placed at each supply pin to ground if split supplies are to

supply rail. See Figure 1 for a complete tuned power supply

bypass methodology.

Printed Circuit Board Layout

For good AC performance, parasitic capacitance should be

kept to minimum. Use of wire wound resistors should be

avoided because of their additional series inductance. Use

of sockets should also be avoided if possible. Sockets add

parasitic inductance and capacitance that can result in

compromised performance. Minimizing parasitic capacitance

at the amplifier's inverting input pin is very important. The

feedback resistor should be placed very close to the

inverting input pin. Strip line design techniques are

recommended for the signal traces.

PD

MAX

T

JMAX

T

AMAX

–

Θ

JA

---------------------------------------------

=

(EQ. 2)

PD

MAX

V

S

I

SMAX

V

S

V

OUTi

–

()

i1

=

n

∑

V

OUTi

R

Li

-----------------

×

+

×

=

(EQ. 3)

PD

MAX

V

S

I

SMAX

V

OUTi

V

S

–

()

i1

=

n

∑

I

LOADi

×

+

×

=

(EQ. 4)

EL5152, EL5153, EL5252, EL5455