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ISL6269BIRZ Datasheet(PDF) 11 Page - Intersil Corporation |
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ISL6269BIRZ Datasheet(HTML) 11 Page - Intersil Corporation |
11 / 14 page 11 FN6280.1 August 7, 2006 General Application Design Guide This design guide is intended to provide a high-level explanation of the steps necessary to create a single-phase power converter. It is assumed that the reader is familiar with many of the basic skills and techniques referenced below. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts. Selecting the LC Output Filter The duty cycle of an ideal buck converter is a function of the input and the output voltage. This relationship is written as: The output inductor peak-to-peak ripple current is written as: A typical step-down DC/DC converter will have an IPP of 20% to 40% of the maximum DC output load current. The value of IPP is selected based upon several criteria such as MOSFET switching loss, inductor core loss, and the resistive loss of the inductor winding. The DC copper loss of the inductor can be estimated by: Where ILOAD is the converter output DC current. The copper loss can be significant so attention has to be given to the DCR selection. Another factor to consider when choosing the inductor is its saturation characteristics at elevated temperature. A saturated inductor could cause destruction of circuit components, as well as nuisance OCP faults. A DC/DC buck regulator must have output capacitance COUT into which ripple current IPP can flow. Current IPP develops a corresponding ripple voltage VPP across COUT, which is the sum of the voltage drop across the capacitor ESR and of the voltage change stemming from charge moved in and out of the capacitor. These two voltages are written as: and If the output of the converter has to support a load with high pulsating current, several capacitors will need to be paralleled to reduce the total ESR until the required VPP is achieved. The inductance of the capacitor can cause a brief voltage dip if the load transient has an extremely high slew rate. Low inductance capacitors constructed with reverse package geometry are available. A capacitor dissipates heat as a function of RMS current and frequency. Be sure that IPP is shared by a sufficient quantity of paralleled capacitors so that they operate below the maximum rated RMS current at FSW. Take into account that the rated value of a capacitor can fade as much as 50% as the DC voltage across it increases. Selection of the Input Capacitor The important parameters for the bulk input capacitance are the voltage rating and the RMS current rating. For reliable operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and capable of supplying the RMS current required by the switching circuit. Their voltage rating should be at least 1.25 times greater than the maximum input voltage, while a voltage rating of 1.5 times is a preferred rating. Figure 6 is a graph of the input RMS ripple current, normalized relative to output load current, as a function of duty cycle that is adjusted for converter efficiency. The ripple current calculation is written as: Where: -IMAX is the maximum continuous ILOAD of the converter - x is a multiplier (0 to 1) corresponding to the inductor peak-to-peak ripple amplitude expressed as a percentage of IMAX (0% to 100%) - D is the duty cycle that is adjusted to take into account the efficiency of the converter which is written as: In addition to the bulk capacitance, some low ESL ceramic capacitance is recommended to decouple between the drain of the high-side MOSFET and the source of the low-side MOSFET. D V OUT V IN ---------------- = (EQ. 9) (EQ. 10) I PP V OUT 1D – () • F SW LOUT • -------------------------------------- = (EQ. 11) P COPPER I LOAD 2 DCR • = ∆V ESR I PP E • SR = (EQ. 12) ∆V C I PP 8C OUT F • SW • --------------------------------------- = (EQ. 13) (EQ. 14) I IN_RMS I MAX 2 DD 2 – () ⋅ () xI MAX 2 D 12 ------ ⋅⋅ ⎝⎠ ⎛⎞ + I MAX ----------------------------------------------------------------------------------------------------- = D V OUT V IN EFF ⋅ -------------------------- = 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 FIGURE 6. NORMALIZED RMS INPUT CURRENT FOR x = 0.8 DUTY CYCLE x = 1 x = 0.75 x = 0.50 x = 0.25 x = 0 ISL6269B |
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