3

FN6413.0

December 21, 2006

22

SYSRST#

System Reset I/O

As an input, allows for immediate and unconditional latch-off of all GATE outputs when driven low. This pin

can also be used to initiate the programmed sequence with ‘zero’ wait (no 10ms stabilization delay) from

input signal on this pin being driven high to first GATE.

As an output when there is a UV condition this pin pulls low. If common to other SYSRST# pins in a multiple

IC configuration it will cause immediate and unconditional latch-off of all other GATEs on all other ISL872x

sequencers.

This pin is released to go high once all UVLO and enable conditions are satisfied and is pulled low

concurrent with the last GATE being turned off after EN disabled.

9,11,

19

No Connect

No Connect

No Connect

PIN

#

PIN NAME

FUNCTION

DESCRIPTION

ISL8723, ISL8724