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ISL8701 Datasheet(PDF) 4 Page - Intersil Corporation |
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ISL8701 Datasheet(HTML) 4 Page - Intersil Corporation |
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4 / 13 page  4 FN9250.2 March 21, 2008 BIAS IC Supply Current IVIN_2.2V VIN = 2.2V - 191 - µA IVIN_12V VIN = 12V - 246 400 µA IVIN_24V VIN = 24V - 286 - µA VIN Power On Reset VIN_POR VIN low to high - 2.08 2.5 V Pin Descriptions PIN NUMBER PIN NAME FUNCTION DESCRIPTION ISL8700 ISL8701 ISL8702 NA 1 NA ENABLE#_D Active low open drain sequenced output. Sequenced on after ENABLE#_C and first output to sequence off for the ISL8701. Tracks VIN upon bias. 1 NA 1 ENABLE_D Active high open drain sequenced output. Sequenced on after ENABLE_C and first output to sequence off for the ISL8700, ISL8702. Pulls low with VIN < 1V. NA 2 NA ENABLE#_C Active low open drain sequenced output. Sequenced on after ENABLE#_B and sequenced off after ENABLE#_D for the ISL8701. Tracks VIN upon bias. 2 NA 2 ENABLE_C Active high open drain sequenced output. Sequenced on after ENABLE_B and sequenced off after ENABLE_D for the ISL8700, ISL8702. Pulls low with VIN < 1V. NA 3 NA ENABLE#_B Active low open drain sequenced output. Sequenced on after ENABLE#_A and sequenced off after ENABLE#_C for the ISL8701. Tracks VIN upon bias. 3 NA 3 ENABLE_B Active high open drain sequenced output. Sequenced on after ENABLE_A and sequenced off after ENABLE_C for the ISL8700, ISL8702. Pulls low with VIN < 1V. NA 4 NA ENABLE#_A Active low open drain sequenced output. Sequenced on after CTIME period and sequenced off after ENABLE#_B for the ISL8701. Tracks VIN upon bias. 4 NA 4 ENABLE_A Active high open drain sequenced output. Sequenced on after CTIME period and sequenced off after ENABLE_B for the ISL8700, ISL8702. Pulls low with VIN < 1V. 5 5 5 OV The voltage on this pin must be under its 1.22V Vth or the four ENABLE outputs will be immediately pulled down. Conversely the 4 ENABLE# outputs will be released to be pulled high via external pull ups. 6 6 6 UV The voltage on this pin must be over its 1.22V Vth or the four ENABLE outputs will be immediately pulled down. Conversely the 4 ENABLE# outputs will be released to be pulled high via external pull ups. 7 7 7 GND IC ground. NA NA 8 FAULT The VIN voltage when not within the desired UV to OV window will cause FAULT to be released to be pulled high to a voltage equal to or less than VIN via an external resistor. NA NA 9 SEQ_EN This pin provides a sequence on signal input with a high input. Internally pulled high to VIN. NA NA NA SEQ_EN# This pin provides a sequence on signal input with a low input. Internally pulled high to VIN. 10 10 10 TIME This pin provides a 2.6µA current output so that an adjustable VIN valid to sequencing on and off start delay period is created with a capacitor to ground. 11 11 11 TB A resistor connected from this pin to ground determines the time delay from ENABLE_A being active to ENABLE _B being active on turn-on and also going inactive on turn-off via the SEQ_IN input. 12 12 12 TC A resistor connected from this pin to ground determines the time delay from ENABLE_B being active to ENABLE _C being active on turn-on and also going inactive on turn-off via the SEQ_IN input. 13 13 13 TD A resistor connected from this pin to ground determines the time delay from ENABLE_C being active to ENABLE _D being active on turn-on and also going inactive on turn-off via the SEQ_IN input. 14 14 14 VIN IC Bias Pin Nominally 2.5V to 24V (2.5V to 12V for ISL8702). This pin requires a 1µF decoupling capacitor close to IC pin. Electrical Specifications Nominal VIN = 2.5V to +24V, TA = TJ = -40°C to +85°C, Unless Otherwise Specified. ISL8702 VIN = 2.5V to +12V (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT ISL8700, ISL8701, ISL8702 |
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