5

FN9250.2

March 21, 2008

Functional Block Diagram

Functional Description

The ISL870x family of ICs provides four delay adjustable

sequenced outputs while monitoring a single distributed voltage

in the nominal range of 2.5V to 24V for both under and

overvoltage. Only when the voltage is in compliance will the

ISL870x initiate the pre-programmed A-B-C-D sequence of the

ENABLE (ISL8700, ISL8702) or ENABLE# (ISL8701) outputs.

Although this IC has a bias range of 2.5V to 24V (12V for

ISL8702) it can monitor any voltage >1.22V via the external

divider if a suitable bias voltage is otherwise provided.

is constantly monitored for compliance via the input voltage

resistor divider and the voltages on the UV and OV pins and

reported by the FAULT output. Internally, voltage regulators

generate 3.5V and 1.17V ±5% voltage rails for internal usage

high or open, the auto sequence of the four ENABLE

(ENABLE#) outputs begins as the TIME pin charges its external

capacitor with a 2.6µA current source. The voltage on TIME is

ENABLE_A is released to go high via an external pull-up

resistor or a pull-up in a DC/DC convertor enable input, for

example. Conversely, ENABLE#_A output will be pulled low at

this time on an ISL8701. The time delay generated by the

external capacitor is to assure continued voltage compliance

within the programmed limits, as during this time any OV or UV

condition will halt the start-up process. TIME capacitor is

Once ENABLE_A is active (either released high on the

ISL8700, ISL8702 or pulled low on the ISL8701), a counter is

started and using the resistor on TB as a timing component, a

delay is generated before ENABLE_B is activated. At this time,

the counter is restarted using the resistor on TC as its timing

component for a separate timed delay until ENABLE_C is

activated. This process is repeated for the resistor on TD to

complete the A-B-C-D sequencing order of the ENABLE or

ENABLE# outputs. At any time during sequencing if an OV or

UV event is registered, all four ENABLE outputs will

immediately return to their reset state; low for ISL8700,

discharged after initial ramp-up thus waiting for subsequent

voltage compliance to restart. Once sequencing is complete,

any subsequently registered UV or OV event will trigger an

immediate and simultaneous reset of all ENABLE or ENABLE#

outputs.

VIN

VOLTAGE

1.17V

INTERNAL VOLTAGE

REGULATOR

VIN (2.2V MIN TO 27V MAX, 2.5V TO 12V FOR ISL8702)

2.0V VIN POR

3.5V

LOGIC

VREG

PROGRAMMABLE

DELAY TIMER

2.6

VIN

TB

TC

TD

ENABLE_A

ENABLE_B

ENABLE_C

ENABLE_D

TIME

GND

FAULT

SEQ_EN

UV

OV

+

-

-

+

eo

VREF

30µs

REFERENCE

ISL8700, ISL8701, ISL8702