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ISL6439EVAL1 Datasheet(PDF) 10 Page - Intersil Corporation |
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ISL6439EVAL1 Datasheet(HTML) 10 Page - Intersil Corporation |
10 / 15 page 10 the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage ∆VOSC. Modulator Break Frequency Equations The compensation network consists of the error amplifier (internal to the ISL6439) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees. The equations below relate the compensation network’s poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 5. Use these guidelines for locating the poles and zeros of the compensation network: 1. Pick gain (R2/R1) for desired converter bandwidth. 2. Place first zero below filter’s double pole (~75% FLC). 3. Place second zero at filter’s double pole. 4. Place first pole at the ESR zero. 5. Place second pole at half the switching frequency. 6. Check gain against error amplifier’s open-loop gain. 7. Estimate phase margin - repeat if necessary. Compensation Break Frequency Equations Figure 6 shows an asymptotic plot of the DC-DC converter’s gain vs frequency. The actual Modulator Gain has a high gain peak due to the high Q factor of the output filter and is not shown in Figure 6. Using the above guidelines should give a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the graph of Figure 6 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin. Component Selection Guidelines Charge Pump Capacitor Selection A capacitor across pins CT1 and CT2 is required to create the proper bias voltage for the ISL6439 when operating the IC from 3.3V. Selecting the proper capacitance value is important so that the bias current draw and the current required by the MOSFET gates do not overburden the FIGURE 5. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN VOUT REFERENCE LO CO ESR VIN ∆VOSC ERROR AMP PWM DRIVER (PARASITIC) ZFB + - REFERENCE R1 R3 R2 C3 C1 C2 COMP VOUT FB ZFB ISL6439 ZIN COMPARATOR DRIVER DETAILED COMPENSATION COMPONENTS PHASE VE/A + - + - ZIN OSC F LC 1 2 π x L O x CO ------------------------------------------ = F ESR 1 2 π x ESR x C O ------------------------------------------- = F Z2 1 2 π x R 1 R 3 + () x C 3 ------------------------------------------------------- = F P1 1 2 π x R 2 x C 1 x C2 C 1 C 2 + ---------------------- --------------------------------------------------------- = F P2 1 2 π x R 3 x C3 ------------------------------------ = F Z1 1 2 π R 2 × C 2 × ---------------------------------- = FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN 100 80 60 40 20 0 -20 -40 -60 FP1 FZ2 10M 1M 100K 10K 1K 100 10 OPEN LOOP ERROR AMP GAIN FZ1 FP2 FLC FESR COMPENSATION FREQUENCY (Hz) GAIN MODULATOR GAIN LOOP GAIN 20 V IN V OSC ---------------- log 20 R2 R1 -------- log ISL6439 |
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