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EL4585CS-T7 Datasheet(PDF) 5 Page - Intersil Corporation |
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EL4585CS-T7 Datasheet(HTML) 5 Page - Intersil Corporation |
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5 / 15 page  5 FN7175.4 September 3, 2009 Timing Diagrams Test Circuit PLL LOCKED CONDITION (PHASE ERROR = 0) OUT OF LOCK CONDITION θE = tθtH × 360° tH = HSYNC PERIOD t θ = PHASE ERROR PERIOD ~200ns ~200ns H-SYNC (INPUT) EXT. DIV. (INPUT OR OUTPUT) ± 50ns tH HSYNC EXT. DIV CHARGE PUMP OFF OFF - + + - t0 TEST CIRCUIT 1 VOUT + - 3 5 VIN 0.1µF 10mVRMS EL4585 |
Similar Part No. - EL4585CS-T7 |
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Similar Description - EL4585CS-T7 |
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