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HS0-303BRH-Q Datasheet(PDF) 3 Page - Intersil Corporation

Part # HS0-303BRH-Q
Description  Radiation Hardened CMOS Dual SPDT Analog Switch
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

HS0-303BRH-Q Datasheet(HTML) 3 Page - Intersil Corporation

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All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6411.1
July 7, 2008
Functional Diagram
Die Characteristics
DIE DIMENSIONS:
2690µm x 5200µm (106 milsx205 mils)
Thickness: 483µm
± 25.4µm (19 mils ± 1 mil)
INTERFACE MATERIALS:
Glassivation:
Type: PSG (Phosphorous Silicon Glass)
Thickness: 8.0kÅ
± 1.0kÅ
Top Metallization:
Type: AlSiCu
Thickness: 16.0kÅ
± 2kÅ
Substrate:
Radiation Hardened Silicon Gate,
Dielectric Isolation
Backside Finish:
Silicon
ASSEMBLY RELATED INFORMATION:
Substrate Potential:
Unbiased (DI)
ADDITIONAL INFORMATION:
Worst Case Current Density:
<2.0 x 105 A/cm2
Transistor Count:
196
Metallization Mask Layout
HS-303ARH, HS-303BRH
N
P
IN
D
TRUTH TABLE
LOGIC
SW1 AND SW2
SW3 AND SW4
0OFF
ON
1ON
OFF
GND
V-
V+
HS-303ARH, HS-303BRH


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