3

FN6981.1

November 19, 2009

Pin Descriptions

PIN NAME

PIN NUMBER

DESCRIPTION

DT

1

Detection Threshold. Reference DC current threshold for input signal power detection. Data

output OUT[k] is muted when the power of the equalized version of IN[k] falls below the

threshold. Tie to ground to disable electrical idle preservation and always enable the limiting

amplifier.

IN1[P,N]

2, 3

Equalizer 1 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least

4GHz frequency response is recommended.

4, 7, 10, 29,

32, 35

Power supply. 1.2V supply voltage. The use of parallel 100pF and 10nF decoupling capacitors to

ground is recommended for each of these pins for broad high-frequency noise suppression.

IN2[P,N]

5, 6

Equalizer 2 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least

4GHz frequency response is recommended.

IN3[P,N]

8, 9

Equalizer 3 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least

4GHz frequency response is recommended.

IN4[P,N]

11, 12

Equalizer 4 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least

4GHz frequency response is recommended.

LOS1

13

LOS indicator 1. High output when equalized IN1 signal is below DT threshold.

LOS2

14

LOS indicator 2. High output when equalized IN2 signal is below DT threshold.

GND

15

Ground

DI

16

Serial data input, CMOS logic. Input for serial data stream to program internal registers

controlling the boost for all four equalizers. Synchronized with clock (CLK) on pin 46. Overrides

the boost setting established on CP control pins. Internally pulled down.

DO

17

Serial data output, CMOS logic. Output of the internal registers controlling the boost for all four

equalizers. Synchronized with clock on pin 46. Equivalent to serial data input on DI but delayed

by 21 clock cycles.

CP3[A,B,C]

18, 19, 20

Control pins for setting equalizer 3. CMOS logic inputs. Pins are read as a 3-digit number to set

the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ

resistor.

CP4[A,B,C]

21, 22, 23

Control pins for setting equalizer 4. CMOS logic inputs. Pins are read as a 3-digit number to set

the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ

resistor.

MODE

24

Boost-level control mode input, CMOS logic. Allows serial programming of internal registers

through pins DI, ENB, and Clk when set HIGH. Resets all internal registers to zero and uses boost

levels set by CP pins when set LOW. If serial programming is not used, this pin should be

grounded.

LOS4

25

LOS indicator 4. High output when equalized IN4 signal is below DT threshold.

LOS3

26

LOS indicator 3. High output when equalized IN3 signal is below DT threshold.

OUT4[N,P]

27, 28

Equalizer 4 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least

4GHz frequency response is recommended.

OUT3[N,P]

30, 31

Equalizer 3 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least

4GHz frequency response is recommended.

OUT2[N,P]

33, 34

Equalizer 2 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least

4GHz frequency response is recommended.

OUT1[N,P]

36, 37

Equalizer 1 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least

4GHz frequency response is recommended.

BGREF

38

External bandgap reference resistor. Recommended value of 6.04kΩ ±1%.

QLx4600-SL30