7

FN6981.1

November 19, 2009

Line Silence-to-Data

Response Time

Time to transition from line silence mode

(muted output) to active data on 20m

24AWG standard twin-axial cable at 5Gb/s

20

ns

8, 11

Time from first bit of ALIGN(0) for SAS

Meritec 24AWG 20m; 3Gb/s

19

ns

12

Timing Difference (SAS)

24AWG 20m

5ns

12

NOTES:

3. After channel loss, differential amplitudes at QLx4600-SL30 inputs must meet the input voltage range specified in “Absolute

Maximum Ratings” on page 5.

5. Output residual jitter is the difference between the total jitter at the lane extender output and the total jitter of the transmitted

media-induced loss only.

7. Rise and fall times measured using a 1GHz clock with a 20ps edge rate.

9. Measured differentially across the data source.

10. During line silence, transmitter noise in excess of this voltage range may result in differential output amplitudes from the

11. The data pattern preceding line silence mode is comprised of the PCIe electrical idle ordered set (EIOS). The data pattern

following line silence mode is comprised of the PCIe electrical idle exit sequence (EIES).

12. The data pattern preceding or following line silence mode is comprised of the SAS-2 ALIGN (0) sequence for OOB signaling at

PARAMETERS

SYMBOL

CONDITION

MIN

TYP

MAX

UNITS NOTES

Serial Bus Timing Characteristics

PARAMETER

SYMBOL

CONDITION

MIN

TYP

MAX

UNITS

CLK Setup Time

From the falling edge of ENB

10

ns

DI Setup Time

Prior to the rising edge of CLK

10

ns

DI Hold Time

From the rising edge of CLK

6

ns

ENB ‘HIGH’

From the falling edge of the last data bit’s CLK

10

ns

Boost Setting Operational

From ENB ‘HIGH’

10

ns

DO Hold Time

From the rising edge of CLK to DO transition

12

ns

Clock Rate

Reference clock for serial bus EQ programming

20

MHz

QLx4600-SL30