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ADC11DS105 Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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ADC11DS105 Datasheet(HTML) 6 Page - National Semiconductor (TI) |
6 / 24 page Pin No. Symbol Equivalent Circuit Description 53 SDO Serial Data-Out: Serial data are shifted out of the device on this pin while SCSb signal is asserted. This output is in tri-state mode when SCSb is deasserted. 46 30 ORA ORB Overrange. These CMOS outputs are asserted logic-high when their respective channel’s data output is out-of-range in either high or low direction. 24 DLL_Lock DLL_Lock Output. When the internal DLL is locked to the input CLK, this pin outputs a logic high. If the input CLK is changed abruptly, the internal DLL may become unlocked and this pin will output a logic low. Cycle Reset_DLL (pin 28) to re-lock the DLL to the input CLK. ANALOG POWER 8, 16, 17, 58, 60 V A Positive analog supply pins. These pins should be connected to a quiet source and be bypassed to AGND with 0.1 µF capacitors located close to the power pins. 1, 4, 12, 15, Exposed Pad AGND The ground return for the analog supply. The exposed pad on back of package must be soldered to ground plane to ensure rated performance. DIGITAL POWER 26, 40, 50 V DR Positive driver supply pin for the output drivers. This pin should be connected to a quiet voltage source and be bypassed to DRGND with a 0.1 µF capacitor located close to the power pin. 25, 39, 51 DRGND The ground return for the digital output driver supply. This pins should be connected to the system digital ground, but not be connected in close proximity to the ADC's AGND pins. www.national.com 6 |
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