74AHC_AHCT595_4

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 04 — 11 August 2009

4 of 21

NXP Semiconductors

74AHC595; 74AHCT595

8-bit serial-in/serial-out or parallel-out shift register with output latches

6.

Pinning information

6.1 Pinning

6.2 Pin description

Fig 5.

Pin configuration SO16 and TSSOP16

Fig 6.

Pin configuration DHVQFN16

74AHC595

74AHCT595

Q1

Q2

Q0

Q3

DS

Q4

OE

Q5

STCP

Q6

SHCP

Q7

MR

GND

Q7S

001aae538

1

2

3

4

5

6

7

8

10

9

12

11

14

13

16

15

001aae483

74AHC595

74AHCT595

Q7

MR

Q6

SHCP

Q5

STCP

Q4

OE

Q3

DS

Q2

Q0

Transparent top view

7

10

6

11

5

12

4

13

3

14

2

15

terminal 1

index area

Table 2.

Pin description

Symbol

Pin

Description

Q1

1

parallel data output 1

Q2

2

parallel data output 2

Q3

3

parallel data output 3

Q4

4

parallel data output 4

Q5

5

parallel data output 5

Q6

6

parallel data output 6

Q7

7

parallel data output 7

GND

8

ground (0 V)

Q7S

9

serial data output

MR

10

master reset (active LOW)

SHCP

11

shift register clock input

STCP

12

storage register clock input

OE

13

output enable input (active LOW)

DS

14

serial data input

Q0

15

parallel data output 0

16

supply voltage